Mesa (main): intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP

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Module: Mesa
Branch: main
Commit: e9b509755b4e1621274ff80117ad9858795579d4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b509755b4e1621274ff80117ad9858795579d4

Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date:   Tue Oct  9 14:14:15 2018 -0700

intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP

On XeHP+, Binding Table Pointers are an offset relative to the Surface
State Base Address anymore. Instead, they are relative to the State
Binding Table Pool Address, which is set by the command above.

We emit that command (pointing to the same address as the Surface
State Base Addresss), and everything should stay working as before.

Reworks:
 * Jordan: Add iris
 * Jordan: Drop i965
 * Ken: Set MOCS to avoid a major perf impact. (Found by Felix DeGrood.)
 * Jordan: Shrink size from 2MiB to actual iris, anv usage
 * Lionel: Add BINDING_TABLE_POOL_BLOCK_SIZE

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4995
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
[jordan.l.justen at intel.com: Add Iris, adjust sizes]

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>

---

 src/gallium/drivers/iris/iris_state.c | 11 +++++++++++
 src/intel/vulkan/genX_cmd_buffer.c    | 13 +++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 91bf74a7b4d..be7feff07bd 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5387,6 +5387,17 @@ iris_update_surface_base_address(struct iris_batch *batch,
       emit_pipeline_select(batch, GPGPU);
 #endif
 
+   if (GFX_VERx10 >= 125) {
+      iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
+         btpa.BindingTablePoolBaseAddress = ro_bo(binder->bo, 0);
+         btpa.BindingTablePoolBufferSize = IRIS_BINDER_SIZE / 4096;
+#if GFX_VERx10 < 125
+         btpa.BindingTablePoolEnable = true;
+#endif
+         btpa.MOCS = mocs;
+      }
+   }
+
    flush_after_state_base_change(batch);
    iris_batch_sync_region_end(batch);
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 22f89403841..059b1a7751e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -213,6 +213,19 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
       genX(flush_pipeline_select)(cmd_buffer, gfx12_wa_pipeline);
 #endif
 
+#if GFX_VERx10 >= 125
+   anv_batch_emit(
+      &cmd_buffer->batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
+      btpa.BindingTablePoolBaseAddress =
+         anv_cmd_buffer_surface_base_address(cmd_buffer);
+      btpa.BindingTablePoolBufferSize = BINDING_TABLE_POOL_BLOCK_SIZE / 4096;
+#if GFX_VERx10 < 125
+      btpa.BindingTablePoolEnable = true;
+#endif
+      btpa.MOCS = mocs;
+   }
+#endif
+
    /* After re-setting the surface state base address, we have to do some
     * cache flusing so that the sampler engine will pick up the new
     * SURFACE_STATE objects and binding tables. From the Broadwell PRM,