Mesa (main): radv: fix clears with value of "1" and different DCC signedness

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Module: Mesa
Branch: main
Commit: 34151f9be94ceeafdf46b6c95926d3d326930725
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=34151f9be94ceeafdf46b6c95926d3d326930725

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Dec 16 15:40:38 2021 +0100

radv: fix clears with value of "1" and different DCC signedness

For example, if the driver clears a view of SINT with 127 and the image
format is UNORM, the hw fills "1" instead of the clear value
(127.0f / 255.0f). This CB feature is GFX9+ only.

This should fix test_typed_srv_cast_clear from vkd3d-proton once it
correctly sets the MUTABLE flag (which is still buggy as of c0a3fa8a).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5676
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14228>

---

 src/amd/vulkan/radv_cmd_buffer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c20e75eb5be..2fbd7d4a6a3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2473,6 +2473,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
    int i;
    struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
    const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+   bool disable_constant_encode_ac01 = false;
 
    for (i = 0; i < 8; ++i) {
       if (i >= subpass->color_count ||
@@ -2495,6 +2496,14 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
                                in_render_loop, cmd_buffer->state.attachments[idx].disable_dcc);
 
       radv_load_color_clear_metadata(cmd_buffer, iview, i);
+
+      if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
+          iview->image->dcc_sign_reinterpret) {
+         /* Disable constant encoding with the clear value of "1" with different DCC signedness
+          * because the hardware will fill "1" instead of the clear value.
+          */
+         disable_constant_encode_ac01 = true;
+      }
    }
 
    if (subpass->depth_stencil_attachment) {
@@ -2572,6 +2581,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
       radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
                              S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class <= GFX9) |
                                 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
+                                S_028424_DISABLE_CONSTANT_ENCODE_AC01(disable_constant_encode_ac01) |
                                 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
    }