Mesa (master): st/mesa: do scissored clears on depth/stencil as well when supported

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Module: Mesa
Branch: master
Commit: 5088caa119739a1833e3d26edb7cd58acc161c38
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5088caa119739a1833e3d26edb7cd58acc161c38

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sun Feb  7 15:17:00 2021 -0500

st/mesa: do scissored clears on depth/stencil as well when supported

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Tested-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8905>

---

 src/mesa/state_tracker/st_cb_clear.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c
index 4ff77a6b681..f714c89e3db 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -479,23 +479,27 @@ st_Clear(struct gl_context *ctx, GLbitfield mask)
       struct st_renderbuffer *strb = st_renderbuffer(depthRb);
 
       if (strb->surface && ctx->Depth.Mask) {
-         if (is_scissor_enabled(ctx, depthRb) ||
+         bool scissor = is_scissor_enabled(ctx, depthRb);
+         if ((scissor && !st->can_scissor_clear) ||
              is_window_rectangle_enabled(ctx))
             quad_buffers |= PIPE_CLEAR_DEPTH;
          else
             clear_buffers |= PIPE_CLEAR_DEPTH;
+         have_scissor_buffers |= scissor && st->can_scissor_clear;
       }
    }
    if (mask & BUFFER_BIT_STENCIL) {
       struct st_renderbuffer *strb = st_renderbuffer(stencilRb);
 
       if (strb->surface && !is_stencil_disabled(ctx, stencilRb)) {
-         if (is_scissor_enabled(ctx, stencilRb) ||
+         bool scissor = is_scissor_enabled(ctx, stencilRb);
+         if ((scissor && !st->can_scissor_clear) ||
              is_window_rectangle_enabled(ctx) ||
              is_stencil_masked(ctx, stencilRb))
             quad_buffers |= PIPE_CLEAR_STENCIL;
          else
             clear_buffers |= PIPE_CLEAR_STENCIL;
+         have_scissor_buffers |= scissor && st->can_scissor_clear;
       }
    }