Mesa (master): ac/gpu_info: inline get_l2_cache_size and set cache sizes farther down

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Module: Mesa
Branch: master
Commit: 16cf791861562a4563b2ae6d414d776b1f5eb6be
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=16cf791861562a4563b2ae6d414d776b1f5eb6be

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Feb  4 01:18:12 2021 -0500

ac/gpu_info: inline get_l2_cache_size and set cache sizes farther down

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8892>

---

 src/amd/common/ac_gpu_info.c | 74 +++++++++++++++++++++++---------------------
 1 file changed, 38 insertions(+), 36 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 7d75727d71b..9739ee93f9b 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -236,39 +236,6 @@ static uint64_t fix_vram_size(uint64_t size)
    return align64(size, 256 * 1024 * 1024);
 }
 
-static uint32_t get_l2_cache_size(enum radeon_family family)
-{
-   switch (family) {
-   case CHIP_KABINI:
-   case CHIP_STONEY:
-      return 128 * 1024;
-   case CHIP_OLAND:
-   case CHIP_HAINAN:
-   case CHIP_ICELAND:
-      return 256 * 1024;
-   case CHIP_PITCAIRN:
-   case CHIP_VERDE:
-   case CHIP_BONAIRE:
-   case CHIP_KAVERI:
-   case CHIP_POLARIS12:
-   case CHIP_CARRIZO:
-      return 512 * 1024;
-   case CHIP_TAHITI:
-   case CHIP_TONGA:
-      return 768 * 1024;
-      break;
-   case CHIP_HAWAII:
-   case CHIP_POLARIS11:
-      return 1024 * 1024;
-   case CHIP_FIJI:
-   case CHIP_POLARIS10:
-      return 2048 * 1024;
-      break;
-   default:
-      return 4096 * 1024;
-   }
-}
-
 static bool
 has_tmz_support(amdgpu_device_handle dev,
                 struct radeon_info *info,
@@ -628,9 +595,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->vram_bit_width = amdinfo->vram_bit_width;
    info->ce_ram_size = amdinfo->ce_ram_size;
 
-   info->l2_cache_size = get_l2_cache_size(info->family);
-   info->l1_cache_size = 16384;
-
    /* Set which chips have uncached device memory. */
    info->has_l2_uncached = info->chip_class >= GFX9;
 
@@ -711,6 +675,44 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
       info->tcc_cache_line_size = 64;
       info->num_tcc_blocks = info->max_tcc_blocks;
    }
+
+   switch (info->family) {
+   case CHIP_KABINI:
+   case CHIP_STONEY:
+      info->l2_cache_size = 128 * 1024;
+      break;
+   case CHIP_OLAND:
+   case CHIP_HAINAN:
+   case CHIP_ICELAND:
+      info->l2_cache_size = 256 * 1024;
+      break;
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_BONAIRE:
+   case CHIP_KAVERI:
+   case CHIP_POLARIS12:
+   case CHIP_CARRIZO:
+      info->l2_cache_size = 512 * 1024;
+      break;
+   case CHIP_TAHITI:
+   case CHIP_TONGA:
+      info->l2_cache_size = 768 * 1024;
+      break;
+   case CHIP_HAWAII:
+   case CHIP_POLARIS11:
+      info->l2_cache_size = 1024 * 1024;
+      break;
+   case CHIP_FIJI:
+   case CHIP_POLARIS10:
+      info->l2_cache_size = 2048 * 1024;
+      break;
+   default:
+      info->l2_cache_size = 4096 * 1024;
+      break;
+   }
+
+   info->l1_cache_size = 16384;
+
    info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg;
    info->gb_addr_config = amdinfo->gb_addr_cfg;
    if (info->chip_class >= GFX9) {