Mesa (master): genxml: Add PIPE_CONTROL protected memory bits

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Thu Feb 18 10:44:34 UTC 2021


Module: Mesa
Branch: master
Commit: e484478727ca51f6a80ab4f572e11c7e0c9ceaaa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e484478727ca51f6a80ab4f572e11c7e0c9ceaaa

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Dec 18 11:35:30 2020 +0200

genxml: Add PIPE_CONTROL protected memory bits

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9127>

---

 src/intel/genxml/gen12.xml  | 2 ++
 src/intel/genxml/gen125.xml | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 257be4b8e6f..f08d4ffa8f4 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6413,6 +6413,7 @@
     <field name="Global Snapshot Count Reset" start="51" end="51" type="bool"/>
     <field name="Command Streamer Stall Enable" start="52" end="52" type="bool"/>
     <field name="Store Data Index" start="53" end="53" type="uint"/>
+    <field name="Protected Memory Enable" start="54" end="54" type="bool"/>
     <field name="LRI Post Sync Operation" start="55" end="55" type="uint">
       <value name="No LRI Operation" value="0"/>
       <value name="MMIO Write Immediate Data" value="1"/>
@@ -6422,6 +6423,7 @@
       <value name="GGTT" value="1"/>
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
+    <field name="Protected Memory Disable" start="59" end="59" type="bool"/>
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
     <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 88ba378be5f..ef2aa1b0409 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -6343,6 +6343,7 @@
     <field name="Global Snapshot Count Reset" start="51" end="51" type="bool"/>
     <field name="Command Streamer Stall Enable" start="52" end="52" type="bool"/>
     <field name="Store Data Index" start="53" end="53" type="uint"/>
+    <field name="Protected Memory Enable" start="54" end="54" type="bool"/>
     <field name="LRI Post Sync Operation" start="55" end="55" type="uint">
       <value name="No LRI Operation" value="0"/>
       <value name="MMIO Write Immediate Data" value="1"/>
@@ -6352,6 +6353,7 @@
       <value name="GGTT" value="1"/>
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
+    <field name="Protected Memory Disable" start="59" end="59" type="bool"/>
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
     <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>



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