Mesa (staging/21.0): intel/compiler: Enable the ability to emit CMPN instructions

[GitLab Mirror]

Module: Mesa
Branch: staging/21.0
Commit: 674a5368258951ecc549a8f121f30ee6c6c36447
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=674a5368258951ecc549a8f121f30ee6c6c36447

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Sat Feb 13 14:11:30 2021 -0800

intel/compiler: Enable the ability to emit CMPN instructions

v2: Move checks to the EU validator.  Suggested by Jason.

Fixes: 2f2c00c7279 ("i965: Lower min/max after optimization on Gen4/5.")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9027>
(cherry picked from commit 6c8e2e9317fe221eb360c37021e0a43155701a06)

---

 .pick_status.json                         |  2 +-
 src/intel/compiler/brw_eu.h               |  6 ++++++
 src/intel/compiler/brw_eu_emit.c          | 30 ++++++++++++++++++++++++++++++
 src/intel/compiler/brw_fs_generator.cpp   | 12 ++++++++++++
 src/intel/compiler/brw_vec4_generator.cpp |  3 +++
 5 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 7aa4dfe0b37..d73662aa697 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -364,7 +364,7 @@
         "description": "intel/compiler: Enable the ability to emit CMPN instructions",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "2f2c00c7279e7c43e520e21de1781f8cec263e92"
     },
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index fbcb9a03060..bc1f4d0cebe 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -1281,6 +1281,12 @@ void brw_CMP(struct brw_codegen *p,
 	     struct brw_reg src0,
 	     struct brw_reg src1);
 
+void brw_CMPN(struct brw_codegen *p,
+              struct brw_reg dest,
+              unsigned conditional,
+              struct brw_reg src0,
+              struct brw_reg src1);
+
 void
 brw_untyped_atomic(struct brw_codegen *p,
                    struct brw_reg dst,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index bac3e7f0892..5002ddd4910 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1986,6 +1986,36 @@ void brw_CMP(struct brw_codegen *p,
    }
 }
 
+void brw_CMPN(struct brw_codegen *p,
+              struct brw_reg dest,
+              unsigned conditional,
+              struct brw_reg src0,
+              struct brw_reg src1)
+{
+   const struct gen_device_info *devinfo = p->devinfo;
+   brw_inst *insn = next_insn(p, BRW_OPCODE_CMPN);
+
+   brw_inst_set_cond_modifier(devinfo, insn, conditional);
+   brw_set_dest(p, insn, dest);
+   brw_set_src0(p, insn, src0);
+   brw_set_src1(p, insn, src1);
+
+   /* Page 166 of the Ivy Bridge PRM Volume 4 part 3 (Execution Unit ISA)
+    * says:
+    *
+    *    If the destination is the null register, the {Switch} instruction
+    *    option must be used.
+    *
+    * Page 77 of the Haswell PRM Volume 2b contains the same text.
+    */
+   if (devinfo->gen == 7) {
+      if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+          dest.nr == BRW_ARF_NULL) {
+         brw_inst_set_thread_control(devinfo, insn, BRW_THREAD_SWITCH);
+      }
+   }
+}
+
 /***********************************************************************
  * Helpers for the various SEND message types:
  */
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 9465907cc60..709f4b0770e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2117,6 +2117,18 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
          }
          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 	 break;
+      case BRW_OPCODE_CMPN:
+         if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
+             dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
+            /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
+             * implemented in the compiler is not sufficient. Overriding the
+             * type when the destination is the null register is necessary but
+             * not sufficient by itself.
+             */
+            dst.type = BRW_REGISTER_TYPE_D;
+         }
+         brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
+         break;
       case BRW_OPCODE_SEL:
 	 brw_SEL(p, dst, src[0], src[1]);
 	 break;
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 38c841fbaf2..a2e84397921 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1594,6 +1594,9 @@ generate_code(struct brw_codegen *p,
       case BRW_OPCODE_CMP:
          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
          break;
+      case BRW_OPCODE_CMPN:
+         brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
+         break;
       case BRW_OPCODE_SEL:
          brw_SEL(p, dst, src[0], src[1]);
          break;