Mesa (master): intel/dev: Implement pixel pipe subslice counting for Gen12+.

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Module: Mesa
Branch: master
Commit: e2ef1c46760ba6996fd49f5fc56d56e1af8d2220
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2ef1c46760ba6996fd49f5fc56d56e1af8d2220

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Dec  4 12:39:39 2020 -0800

intel/dev: Implement pixel pipe subslice counting for Gen12+.

Unlike Gen11, Gen12 hardware supports up to three pixel pipes per
slice.

Unfortunately the kernel interface is somewhat inconsistent between
Gen11 and Gen12: I915_PARAM_SUBSLICE_MASK returns a mask of enabled
*dual* subslices since TGL, so there is half the number of bits per
pixel pipe in the mask.  This is worked around here so we're able to
calculate the correct size of each pixel pipe, but the result is
returned in dual subslice units, inheriting the inconsistency from the
kernel -- Reason is that as of now all our Gen12 subslice counts
returned by gen_device_info.c are really dual subslice counts, and the
num_eu_per_subslice counts are also scaled accordingly, so it seems
like it would only make the matter worse if I fixed the units of this
field only without also fixing the rest.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>

---

 src/intel/dev/gen_device_info.c | 24 +++++++++++++-----------
 src/intel/dev/gen_device_info.h |  2 +-
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index e75ad3ab482..5769c6c7625 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -1089,20 +1089,22 @@ update_from_topology(struct gen_device_info *devinfo,
    }
    assert(n_subslices > 0);
 
-   if (devinfo->gen == 11) {
-      /* On ICL we only have one slice */
+   if (devinfo->gen >= 11) {
+      /* On current ICL+ hardware we only have one slice. */
       assert(devinfo->slice_masks == 1);
 
-      /* Count the number of subslices on each pixel pipe. Assume that
-       * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
+      /* Count the number of subslices on each pixel pipe. Assume that every
+       * contiguous group of 4 subslices in the mask belong to the same pixel
+       * pipe.  However note that on TGL the kernel returns a mask of enabled
+       * *dual* subslices instead of actual subslices somewhat confusingly, so
+       * each pixel pipe only takes 2 bits in the mask even though it's still
+       * 4 subslices.
        */
-      unsigned subslices = devinfo->subslice_masks[0];
-      unsigned ss = 0;
-      while (subslices > 0) {
-         if (subslices & 1)
-            devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
-         subslices >>= 1;
-         ss++;
+      const unsigned ppipe_bits = devinfo->gen >= 12 ? 2 : 4;
+      for (unsigned p = 0; p < GEN_DEVICE_MAX_PIXEL_PIPES; p++) {
+         const unsigned ppipe_mask = BITFIELD_RANGE(p * ppipe_bits, ppipe_bits);
+         devinfo->ppipe_subslices[p] =
+            __builtin_popcount(devinfo->subslice_masks[0] & ppipe_mask);
       }
    }
 
diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
index 09eced3e3e3..166539c75e2 100644
--- a/src/intel/dev/gen_device_info.h
+++ b/src/intel/dev/gen_device_info.h
@@ -39,7 +39,7 @@ struct drm_i915_query_topology_info;
 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gen12 */
-#define GEN_DEVICE_MAX_PIXEL_PIPES      (2)  /* Maximum on gen11 */
+#define GEN_DEVICE_MAX_PIXEL_PIPES      (3)  /* Maximum on gen12 */
 
 /**
  * Intel hardware information and quirks