Mesa (master): radv: Use VRAM for upload buffers if entire VRAM is CPU-visible.

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Module: Mesa
Branch: master
Commit: f06e91d85ab602a0a906f8afc405c0d027b547f0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f06e91d85ab602a0a906f8afc405c0d027b547f0

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Dec  8 00:25:56 2020 +0100

radv: Use VRAM for upload buffers if entire VRAM is CPU-visible.

Not doing this for APUs because spilling is quite likely, due to
overall VRAM pressure.

Also adding a flag to disable for performance debugging.

Finally adds some memset for places where we depended on the memory
being initialized to zero, which we won't get with VRAM anymore.
(I think these places should stop depending on it since it hides
 issues with executing the cmdbuffer multiple times, but this
  preserves behavior)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7979>

---

 docs/envvars.rst                    |  2 ++
 src/amd/vulkan/radv_cmd_buffer.c    | 14 +++++++++++++-
 src/amd/vulkan/radv_debug.h         |  1 +
 src/amd/vulkan/radv_device.c        |  1 +
 src/amd/vulkan/radv_radeon_winsys.h |  2 ++
 5 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/docs/envvars.rst b/docs/envvars.rst
index 9acc1cef3e4..3e9e1219e23 100644
--- a/docs/envvars.rst
+++ b/docs/envvars.rst
@@ -631,6 +631,8 @@ RADV driver environment variables
       enable wave32 for vertex/tess/geometry shaders (GFX10+)
    ``localbos``
       enable local BOs
+   ``nosam``
+      disable optimizations that get enabled when all VRAM is CPU visible.
    ``pswave32``
       enable wave32 for pixel shaders (GFX10+)
    ``tccompatcmask``
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 0d91b67f2c2..6d8dc755b40 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -461,6 +461,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 
 		radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 8, &fence_offset,
 					     &fence_ptr);
+		memset(fence_ptr, 0, 8);
 
 		cmd_buffer->gfx9_fence_va =
 			radv_buffer_get_va(cmd_buffer->upload.upload_bo);
@@ -470,6 +471,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 			/* Allocate a buffer for the EOP bug on GFX9. */
 			radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
 						     &eop_bug_offset, &fence_ptr);
+			memset(fence_ptr, 0, 16 * num_db);
 			cmd_buffer->gfx9_eop_bug_va =
 				radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 			cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
@@ -481,6 +483,15 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 	return cmd_buffer->record_result;
 }
 
+enum radeon_bo_domain
+radv_cmdbuffer_domain(const struct radeon_info *info, uint32_t perftest)
+{
+	return (info->all_vram_visible &&
+	        info->has_dedicated_vram &&
+	        !(perftest & RADV_PERFTEST_NO_SAM)) ?
+		RADEON_DOMAIN_VRAM : RADEON_DOMAIN_GTT;
+}
+
 static bool
 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 				  uint64_t min_needed)
@@ -495,7 +506,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 
 	bo = device->ws->buffer_create(device->ws,
 				       new_size, 4096,
-				       RADEON_DOMAIN_GTT,
+				       radv_cmdbuffer_domain(&device->physical_device->rad_info,
+							     device->instance->perftest_flags),
 				       RADEON_FLAG_CPU_ACCESS|
 				       RADEON_FLAG_NO_INTERPROCESS_SHARING |
 				       RADEON_FLAG_32BIT |
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index e7a578585bb..57c7723164f 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -71,6 +71,7 @@ enum {
 	RADV_PERFTEST_PS_WAVE_32      = 1u << 5,
 	RADV_PERFTEST_GE_WAVE_32      = 1u << 6,
 	RADV_PERFTEST_DFSM            = 1u << 7,
+	RADV_PERFTEST_NO_SAM          = 1u << 8,
 };
 
 bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 94262b32256..0c84d04d625 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -570,6 +570,7 @@ static const struct debug_control radv_perftest_options[] = {
 	{"pswave32", RADV_PERFTEST_PS_WAVE_32},
 	{"gewave32", RADV_PERFTEST_GE_WAVE_32},
 	{"dfsm", RADV_PERFTEST_DFSM},
+	{"nosam", RADV_PERFTEST_NO_SAM},
 	{NULL, 0}
 };
 
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index be5dd62b638..2e79b71bea4 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -376,4 +376,6 @@ static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 	ws->cs_add_buffer(cs, bo);
 }
 
+enum radeon_bo_domain radv_cmdbuffer_domain(const struct radeon_info *info, uint32_t perftest);
+
 #endif /* RADV_RADEON_WINSYS_H */