Mesa (master): zink: use ConstOffset for nir_tex_src_offset
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gitlab-mirror at kemper.freedesktop.org
Tue Jan 5 15:54:09 UTC 2021
Module: Mesa
Branch: master
Commit: b77f43f2539ddac6e334feefaa69a43720f1d2bf
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b77f43f2539ddac6e334feefaa69a43720f1d2bf
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Tue Jan 5 11:58:28 2021 +0100
zink: use ConstOffset for nir_tex_src_offset
Quote from the OpenGL Shading Language spec, version 4.40, section 8.9.2
"Texel Lookup Functions":
> The offset value must be a constant expression.
So, until we start consuming SPIR-V shaders, it seems we don't need to
deal with non-constant offsets.
This means we can avoid lowering this away in some cases.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8327>
---
.../drivers/zink/nir_to_spirv/nir_to_spirv.c | 20 ++++++++++--------
.../drivers/zink/nir_to_spirv/spirv_builder.c | 24 +++++++++++-----------
src/gallium/drivers/zink/zink_compiler.c | 1 -
3 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
index 8e1acff3c20..ffce5df6bc9 100644
--- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
+++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
@@ -2171,7 +2171,7 @@ emit_tex(struct ntv_context *ctx, nir_tex_instr *tex)
assert(tex->texture_index == tex->sampler_index);
SpvId coord = 0, proj = 0, bias = 0, lod = 0, dref = 0, dx = 0, dy = 0,
- offset = 0, sample = 0, tex_offset = 0;
+ const_offset = 0, sample = 0, tex_offset = 0;
unsigned coord_components = 0;
for (unsigned i = 0; i < tex->num_srcs; i++) {
switch (tex->src[i].src_type) {
@@ -2191,7 +2191,8 @@ emit_tex(struct ntv_context *ctx, nir_tex_instr *tex)
break;
case nir_tex_src_offset:
- offset = get_src_int(ctx, &tex->src[i].src);
+ assert(nir_src_is_const(tex->src[i].src));
+ const_offset = get_src_int(ctx, &tex->src[i].src);
break;
case nir_tex_src_bias:
@@ -2332,22 +2333,23 @@ emit_tex(struct ntv_context *ctx, nir_tex_instr *tex)
tex->op == nir_texop_txf_ms ||
tex->op == nir_texop_tg4) {
SpvId image = spirv_builder_emit_image(&ctx->builder, image_type, load);
- if (offset)
- spirv_builder_emit_cap(&ctx->builder, SpvCapabilityImageGatherExtended);
- if (tex->op == nir_texop_tg4)
+
+ if (tex->op == nir_texop_tg4) {
+ if (const_offset)
+ spirv_builder_emit_cap(&ctx->builder, SpvCapabilityImageGatherExtended);
result = spirv_builder_emit_image_gather(&ctx->builder, dest_type,
load, coord, emit_uint_const(ctx, 32, tex->component),
- lod, sample, offset, dref);
- else
+ lod, sample, const_offset, dref);
+ } else
result = spirv_builder_emit_image_fetch(&ctx->builder, dest_type,
- image, coord, lod, sample, offset);
+ image, coord, lod, sample, const_offset);
} else {
result = spirv_builder_emit_image_sample(&ctx->builder,
actual_dest_type, load,
coord,
proj != 0,
lod, bias, dref, dx, dy,
- offset);
+ const_offset);
}
spirv_builder_emit_decoration(&ctx->builder, result,
diff --git a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c
index 505423b0883..47ea144cb1c 100644
--- a/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c
+++ b/src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c
@@ -669,7 +669,7 @@ spirv_builder_emit_image_sample(struct spirv_builder *b,
SpvId dref,
SpvId dx,
SpvId dy,
- SpvId offset)
+ SpvId const_offset)
{
SpvId result = spirv_builder_new_id(b);
@@ -699,9 +699,9 @@ spirv_builder_emit_image_sample(struct spirv_builder *b,
extra_operands[++num_extra_operands] = dy;
operand_mask |= SpvImageOperandsGradMask;
}
- if (offset) {
- extra_operands[++num_extra_operands] = offset;
- operand_mask |= SpvImageOperandsOffsetMask;
+ if (const_offset) {
+ extra_operands[++num_extra_operands] = const_offset;
+ operand_mask |= SpvImageOperandsConstOffsetMask;
}
/* finalize num_extra_operands / extra_operands */
@@ -744,7 +744,7 @@ spirv_builder_emit_image_gather(struct spirv_builder *b,
SpvId component,
SpvId lod,
SpvId sample,
- SpvId offset,
+ SpvId const_offset,
SpvId dref)
{
SpvId result = spirv_builder_new_id(b);
@@ -761,9 +761,9 @@ spirv_builder_emit_image_gather(struct spirv_builder *b,
extra_operands[++num_extra_operands] = sample;
operand_mask |= SpvImageOperandsSampleMask;
}
- if (offset) {
- extra_operands[++num_extra_operands] = offset;
- operand_mask |= SpvImageOperandsOffsetMask;
+ if (const_offset) {
+ extra_operands[++num_extra_operands] = const_offset;
+ operand_mask |= SpvImageOperandsConstOffsetMask;
}
if (dref)
op = SpvOpImageDrefGather;
@@ -796,7 +796,7 @@ spirv_builder_emit_image_fetch(struct spirv_builder *b,
SpvId coordinate,
SpvId lod,
SpvId sample,
- SpvId offset)
+ SpvId const_offset)
{
SpvId result = spirv_builder_new_id(b);
@@ -811,9 +811,9 @@ spirv_builder_emit_image_fetch(struct spirv_builder *b,
extra_operands[++num_extra_operands] = sample;
operand_mask |= SpvImageOperandsSampleMask;
}
- if (offset) {
- extra_operands[++num_extra_operands] = offset;
- operand_mask |= SpvImageOperandsOffsetMask;
+ if (const_offset) {
+ extra_operands[++num_extra_operands] = const_offset;
+ operand_mask |= SpvImageOperandsConstOffsetMask;
}
/* finalize num_extra_operands / extra_operands */
diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c
index d070f607fa1..4f4de8dfff2 100644
--- a/src/gallium/drivers/zink/zink_compiler.c
+++ b/src/gallium/drivers/zink/zink_compiler.c
@@ -431,7 +431,6 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
if (!screen->info.feats.features.shaderImageGatherExtended) {
nir_lower_tex_options tex_opts = {};
tex_opts.lower_tg4_offsets = true;
- tex_opts.lower_txf_offset = true;
NIR_PASS_V(nir, nir_lower_tex, &tex_opts);
}
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