Mesa (master): freedreno/a5xx: Move link_stream_out after VPC_VAR_DISABLE like on a6xx.

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Module: Mesa
Branch: master
Commit: fcecc21832607e33e859ebb65377b5cac882c890
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcecc21832607e33e859ebb65377b5cac882c890

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Jan  4 15:32:56 2021 -0800

freedreno/a5xx: Move link_stream_out after VPC_VAR_DISABLE like on a6xx.

Since we've got issues on a5xx xfb that we don't on a6xx, I've been
looking at making them line up a bit better.  No change on tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8336>

---

 src/gallium/drivers/freedreno/a5xx/fd5_program.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 50641b90f4f..128efc9a2fe 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -367,15 +367,15 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	struct ir3_shader_linkage l = {0};
 	ir3_link_shaders(&l, s[VS].v, s[FS].v, true);
 
-	if (!emit->binning_pass)
-		ir3_link_stream_out(&l, s[VS].v);
-
 	OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
 	OUT_RING(ring, ~l.varmask[0]);  /* VPC_VAR[0].DISABLE */
 	OUT_RING(ring, ~l.varmask[1]);  /* VPC_VAR[1].DISABLE */
 	OUT_RING(ring, ~l.varmask[2]);  /* VPC_VAR[2].DISABLE */
 	OUT_RING(ring, ~l.varmask[3]);  /* VPC_VAR[3].DISABLE */
 
+	if (!emit->binning_pass)
+		ir3_link_stream_out(&l, s[VS].v);
+
 	/* a5xx appends pos/psize to end of the linkage map: */
 	if (pos_regid != regid(63,0))
 		ir3_link_add(&l, pos_regid, 0xf, l.max_loc);