Mesa (master): ir3: use intrinsic builders
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Wed Jan 6 14:51:28 UTC 2021
Module: Mesa
Branch: master
Commit: d46a761e9e36fbf8b9cb6d4483e53354240a7b58
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d46a761e9e36fbf8b9cb6d4483e53354240a7b58
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Fri Jan 1 21:33:35 2021 +0100
ir3: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
---
src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c | 45 +++++++---------------
.../ir3/ir3_nir_lower_load_barycentric_at_sample.c | 19 +--------
src/freedreno/ir3/ir3_nir_lower_tess.c | 24 ++----------
3 files changed, 20 insertions(+), 68 deletions(-)
diff --git a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
index a1c06b90819..8c910f6bacc 100644
--- a/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
+++ b/src/freedreno/ir3/ir3_nir_analyze_ubo_ranges.c
@@ -329,17 +329,11 @@ lower_ubo_load_to_uniform(nir_intrinsic_instr *instr, nir_builder *b,
const_offset = 0;
}
- nir_intrinsic_instr *uniform =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
- uniform->num_components = instr->num_components;
- uniform->src[0] = nir_src_for_ssa(uniform_offset);
- nir_intrinsic_set_base(uniform, const_offset);
- nir_ssa_dest_init(&uniform->instr, &uniform->dest,
- uniform->num_components, instr->dest.ssa.bit_size,
- instr->dest.ssa.name);
- nir_builder_instr_insert(b, &uniform->instr);
+ nir_ssa_def *uniform =
+ nir_load_uniform(b, instr->num_components, instr->dest.ssa.bit_size, uniform_offset, .base = const_offset);
+
nir_ssa_def_rewrite_uses(&instr->dest.ssa,
- nir_src_for_ssa(&uniform->dest.ssa));
+ nir_src_for_ssa(uniform));
nir_instr_remove(&instr->instr);
@@ -556,27 +550,16 @@ ir3_nir_lower_load_const_instr(nir_builder *b, nir_instr *in_instr, void *data)
num_components = DIV_ROUND_UP(num_components, 2);
}
unsigned base = nir_intrinsic_base(instr);
- nir_intrinsic_instr *load =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
- load->num_components = num_components;
- nir_ssa_dest_init(&load->instr, &load->dest,
- load->num_components, 32,
- instr->dest.ssa.name);
-
- load->src[0] = nir_src_for_ssa(nir_imm_int(b,
- const_state->constant_data_ubo));
- load->src[1] = nir_src_for_ssa(nir_iadd_imm(b,
- nir_ssa_for_src(b, instr->src[0], 1), base));
-
- nir_intrinsic_set_align(load,
- nir_intrinsic_align_mul(instr),
- nir_intrinsic_align_offset(instr));
- nir_intrinsic_set_range_base(load, base);
- nir_intrinsic_set_range(load, nir_intrinsic_range(instr));
-
- nir_builder_instr_insert(b, &load->instr);
-
- nir_ssa_def *result = &load->dest.ssa;
+ nir_ssa_def *index = nir_imm_int(b, const_state->constant_data_ubo);
+ nir_ssa_def *offset = nir_iadd_imm(b, nir_ssa_for_src(b, instr->src[0], 1), base);
+
+ nir_ssa_def *result =
+ nir_load_ubo(b, num_components, 32, index, offset,
+ .align_mul = nir_intrinsic_align_mul(instr),
+ .align_offset = nir_intrinsic_align_offset(instr),
+ .range_base = base,
+ .range = nir_intrinsic_range(instr));
+
if (nir_dest_bit_size(instr->dest) == 16) {
result = nir_bitcast_vector(b, result, 16);
result = nir_channels(b, result, BITSET_MASK(instr->num_components));
diff --git a/src/freedreno/ir3/ir3_nir_lower_load_barycentric_at_sample.c b/src/freedreno/ir3/ir3_nir_lower_load_barycentric_at_sample.c
index d9fef618fd4..f705099cfa4 100644
--- a/src/freedreno/ir3/ir3_nir_lower_load_barycentric_at_sample.c
+++ b/src/freedreno/ir3/ir3_nir_lower_load_barycentric_at_sample.c
@@ -35,14 +35,7 @@
static nir_ssa_def *
load_sample_pos(nir_builder *b, nir_ssa_def *samp_id)
{
- nir_intrinsic_instr *load_sp =
- nir_intrinsic_instr_create(b->shader,
- nir_intrinsic_load_sample_pos_from_id);
- load_sp->src[0] = nir_src_for_ssa(samp_id);
- nir_ssa_dest_init(&load_sp->instr, &load_sp->dest, 2, 32, NULL);
- nir_builder_instr_insert(b, &load_sp->instr);
-
- return &load_sp->dest.ssa;
+ return nir_load_sample_pos_from_id(b, 32, samp_id);
}
static nir_ssa_def *
@@ -50,15 +43,7 @@ lower_load_barycentric_at_sample(nir_builder *b, nir_intrinsic_instr *intr)
{
nir_ssa_def *pos = load_sample_pos(b, intr->src[0].ssa);
- nir_intrinsic_instr *load_bary_at_offset =
- nir_intrinsic_instr_create(b->shader,
- nir_intrinsic_load_barycentric_at_offset);
- load_bary_at_offset->src[0] = nir_src_for_ssa(pos);
- nir_ssa_dest_init(&load_bary_at_offset->instr,
- &load_bary_at_offset->dest, 2, 32, NULL);
- nir_builder_instr_insert(b, &load_bary_at_offset->instr);
-
- return &load_bary_at_offset->dest.ssa;
+ return nir_load_barycentric_at_offset(b, 32, pos);
}
static nir_ssa_def *
diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c
index fbb0541b5d9..27bbef9f788 100644
--- a/src/freedreno/ir3/ir3_nir_lower_tess.c
+++ b/src/freedreno/ir3/ir3_nir_lower_tess.c
@@ -253,14 +253,8 @@ lower_block_to_explicit_output(nir_block *block, nir_builder *b, struct state *s
nir_intrinsic_io_semantics(intr).location,
nir_intrinsic_component(intr),
intr->src[1].ssa);
- nir_intrinsic_instr *store =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_shared_ir3);
- store->src[0] = nir_src_for_ssa(intr->src[0].ssa);
- store->src[1] = nir_src_for_ssa(offset);
- store->num_components = intr->num_components;
-
- nir_builder_instr_insert(b, &store->instr);
+ nir_store_shared_ir3(b, intr->src[0].ssa, offset);
break;
}
@@ -644,9 +638,7 @@ emit_tess_epilouge(nir_builder *b, struct state *state)
* TODO we should re-work this to use normal flow control.
*/
- nir_intrinsic_instr *end_patch =
- nir_intrinsic_instr_create(b->shader, nir_intrinsic_end_patch_ir3);
- nir_builder_instr_insert(b, &end_patch->instr);
+ nir_end_patch_ir3(b);
}
void
@@ -705,10 +697,7 @@ ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
/* Insert conditional exit for threads invocation id != 0 */
nir_ssa_def *iid0_cond = nir_ieq_imm(&b, iid, 0);
- nir_intrinsic_instr *cond_end =
- nir_intrinsic_instr_create(shader, nir_intrinsic_cond_end_ir3);
- cond_end->src[0] = nir_src_for_ssa(iid0_cond);
- nir_builder_instr_insert(&b, &cond_end->instr);
+ nir_cond_end_ir3(&b, iid0_cond);
emit_tess_epilouge(&b, &state);
@@ -971,14 +960,9 @@ ir3_nir_lower_gs(nir_shader *shader)
struct nir_block *block = (void *)block_entry->key;
b.cursor = nir_after_block_before_jump(block);
- nir_intrinsic_instr *discard_if =
- nir_intrinsic_instr_create(b.shader, nir_intrinsic_discard_if);
-
nir_ssa_def *cond = nir_ieq_imm(&b, nir_load_var(&b, state.emitted_vertex_var), 0);
- discard_if->src[0] = nir_src_for_ssa(cond);
-
- nir_builder_instr_insert(&b, &discard_if->instr);
+ nir_discard_if(&b, cond);
foreach_two_lists(dest_node, &state.new_outputs, src_node, &state.emit_outputs) {
nir_variable *dest = exec_node_data(nir_variable, dest_node, node);
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