Mesa (master): 38 new commits

Wed Jan 6 16:58:49 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=32a6a13052948cd041ccc27759b412a9a61aa6e2
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Jan 5 12:38:02 2021 -0800

    freedreno/ir3/parser: Fix pre-a6xx stib parsing
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=859c92d7ee6025ff4cf94b530623132d63232457
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Jan 5 12:28:53 2021 -0800

    freedreno/ir3/parser: a6xx ldib/stib parsing
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7ea6ec17875bd6ba2fde3bcabec040bf1e8ac15
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Jan 5 11:39:26 2021 -0800

    freedreno/ir3: Fix pre-a6xx ldgb/stib parsing
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=050a449dbb75eb383c64c29165348cedec40ac34
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Jan 5 10:47:08 2021 -0800

    freedreno/ir3: Explicitly flag disasm test vectors that don't parse
    
    Mark the test cases which aren't supported by ir3_parser.y explicitly,
    so we notice future regressions.  And likewise, fail when we see an
    unexpected pass, so we don't forget to update the test vectors in the
    future as ir3_parser improves.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b073dae5f0dd08fe59b548581bfcec46cb586e01
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Jan 4 12:47:36 2021 -0800

    freedreno/ir3: Fix ldg decoding/parsing
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7e88787f65131311032ac98f7c636ea51316268
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Jan 4 11:30:32 2021 -0800

    freedreno/ir3/parser: Fixup stg parsing and add more tests
    
    The offset can also be a register, in which case we need to shuffle
    around the src order.  Add a few more test vectors to cover each
    permutation (no offset, immed offset, gpr offset).
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6fa130ddadd5d365f9a09f114d73d2374a38c7d
Author: Rob Clark <robdclark at chromium.org>
Date:   Sun Jan 3 10:08:21 2021 -0800

    freedreno/ir3/parser: Add stgb support
    
    Note that this conflicts with `stc` on a6xx+, so a good test that the
    (new) disasm can handle both cases properly.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eddfafae6a454355a99fb1457e10e35b02f0f548
Author: Rob Clark <robdclark at chromium.org>
Date:   Thu Dec 31 11:08:37 2020 -0800

    freedreno/ir3/parser: Add ldgb support
    
    Gives us at least better coverage of pre-a6xx-bindless-ibo instructions.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1746c4d211f3a43092e0a97824e81d9dd4c18c1c
Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 16:58:09 2020 -0800

    freedreno/ir3/parser: Fix pre-a6xx resinfo
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=32539c1afc4cde02595268d2c0ea6196f9600cee
Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 16:04:55 2020 -0800

    freedreno/ir3/parser: Fix atomic support
    
    1) Handle a6xx bindless form
    2) Fix shared vs global encoding
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5479d1d8d8caea48dda58e51d53d492b8d6c3cd
Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 15:18:16 2020 -0800

    freedreno/ir3/parser: Add ldc support
    
    Note that this shows up a slight encoding difference compared to test
    vector extracted from blob deqp runs.  We think these should be dontcare
    bits.  For now, add a note and replace the encoded value in the disasm
    test.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7f141bb353f632ef3a77694e56c92dab8c085f2
Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 15:00:44 2020 -0800

    freedreno/ir3: Add cat5/cat6 nonuniform flag
    
    Not yet used by the compiler, but needed so we don't loose information
    between ir3 parser and instruction encoding.
    
    Currently ignored for cat5, because the uniform vs non-uniform default
    is swapped there.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=101bf686eeb8226dc3dd1dbda2a69d5e9636ddab
Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 13:23:18 2020 -0800

    freedreno/ir3: Disambiguate a6xx+ "bindless" instructions
    
    Add a `.b`.. for the atomic instructions it should be `atomic.b.op` but
    for now put the `.b` at the end to simplify life for the existing disasm
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c55737902c55fe0349919de54e9bf3584f1e7213
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 28 09:05:08 2020 -0800

    freedreno/ir3: Don't leak disk_cache
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=71f902bab9767e33223011bd9cc91e535e8723d0
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 12:35:08 2020 -0800

    freedreno/ir3: Add parsing and assembler testing
    
    In theory we should be able to round-trip from disasm->asm and get a
    bitwise match.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b91319d9520e2d36f9416f7699af46b5faf9d17c
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 11:08:05 2020 -0800

    freedreno/ir3: Tweak ldib/resinfo encoding
    
    The blob is using '0' for the low bit in these (except for ldib where it
    seems to randomly use either '0' or '1').  The upcoming xml based ISA
    spec maps this bit to 'dontcare' in the ldib case.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=99908c8d6d64299b6eed4b01b9601eb2f618255a
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 10:59:15 2020 -0800

    freedreno/ir3/parser: Add initial cat6 IBO instructions
    
    Well, really just resinfo.. dealing with the different ldib/stib syntax
    for a6xx+ vs earlier seems a bit too painful to deal with.  But resinfo
    at least gives us some encoding test coverage of this group of instrs.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9c76fba9d1afe32b0ae62aba6869150db1c9b17
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 09:34:13 2020 -0800

    freedreno/ir3/parser: Relative gpr/const can have modifiers too
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=594b004e0050605180ea3b2778108c2dcefbf369
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 09:15:54 2020 -0800

    freedreno/ir3/parser: Add missing (sat) modifier
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=77552cbdda195df25eca59eadd40d448801681eb
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 09:05:05 2020 -0800

    freedreno/ir3: Don't set bit for dest conversion for p0.c
    
    This appears to be ignored when writing to predicate registers (which I
    guess makes sense, since they are boolean).  So no real harm in setting
    it, other than it makes some of the ir3_parser test vectors not match
    the expected result for encoding.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cdff353618f5f1c9250095c03885ea3f247c71e
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 21 08:44:49 2020 -0800

    freedreno/ir3/parser: Fixup cat5 s2en instructions
    
    Currently ir3 (incl emit_cat5()) expects the samp/tex src register to be
    first.. which requires some fixup for the parser to match.
    
    TODO we might want to revisit the src reg order when adding new instr
    packing/encoding.  For now, lets just make the parser match the rest of
    ir3.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d35c79614e99485ce654ed5352490cc8a0adcc80
Author: Rob Clark <robdclark at chromium.org>
Date:   Sun Dec 20 12:52:08 2020 -0800

    freedreno/ir3/parser: Fix dsxpp/dsypp encoding
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b323491529d959222e97b7530ec1d679f9a071
Author: Rob Clark <robdclark at chromium.org>
Date:   Sun Dec 20 12:35:27 2020 -0800

    freedreno/ir3/parser: Fix cat6 store encoding
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b90a1cf7470a41b7826681e8fd45ab25d61641ac
Author: Rob Clark <robdclark at chromium.org>
Date:   Sun Dec 20 11:05:57 2020 -0800

    freedreno/ir3: Cleanup cat6 load instructions
    
    There was some src2 vs src3 confusion, but since the syntax is like:
    
       ldl.f32 rDst, l[rBase+off], ncomp
    
    it makes more sense to call the offset src2 and ncomp src3, than the
    way we had it.  This is also easier to deal with for the ir3 assembly
    parser.
    
    Also, src_offset was only ever used by the assembly parser, and was
    handled incorrectly in emit_cat6(), resulting that cat6 load instrs
    would not work properly in (for ex) computerator.  Since we are
    cleaning things up, drop src_offset and make the asm parser work in
    the same way as the nir->ir3 frontend.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e272003b17af9c5d9b78e3e31176b89b1b20e7b
Author: Rob Clark <robdclark at chromium.org>
Date:   Sun Dec 20 09:58:45 2020 -0800

    freedreno/ir3: Clean up instruction creation
    
    Convert everything remaining over to the version which takes # of
    register (src + dst) and drop the ir3_instr_create2() version.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d968f46997a6c02dff738d6e1e5c69b3b5e9a31f
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 15:36:24 2020 -0800

    freedreno/ir3/parser: Handle half-immed
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=68be24dd6cfd2ca0f75170bbed9310d53ca9fe0f
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 15:14:26 2020 -0800

    freedreno/ir3/parser: cat1 updates (mova1, movmsk)
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=647d7fc36d3ba74a6d4ed7369d4514130ab5b264
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 14:15:13 2020 -0800

    freedreno/ir3/parser: cat1 instructions can write relative GPR
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b36044d4ff8c9e2d613746d814847d7ddbc2788
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 14:05:58 2020 -0800

    freedreno/ir3/parser: Add new cat0 instructions
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2dc6458563c9886ea61ca3c0f807355def93d6c3
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 13:46:59 2020 -0800

    freedreno/ir3: Various cat0 updates
    
    Update the IR and packer to handle the additional cat0 fields, in
    prep for adding support in the assembler (in prep for adding round
    trip parsing/packing test coverage).
    
    We don't actually use these yet from the ir3 compiler, but at least
    this is one less thing to worry about when we start trying to use
    them.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eec183c1593810d1d2e32c6bc1bdb22a14e55a43
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 13:17:36 2020 -0800

    freedreno/ir3/parser: Reset lexer when input changes
    
    Otherwise, in case of parse errors, the lexer state can still contain
    buffered input from the previous parse.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b2d2bafe4cda1723d704c7bcee9b44f762c9276
Author: Rob Clark <robdclark at chromium.org>
Date:   Sat Dec 19 11:45:31 2020 -0800

    freedreno/ir3: Move assembler error handling
    
    Move out of ir3_parse_asm() so we can re-use it in disasm test for
    round-tripping asm/disasm.  We don't want failures to be fatal (yet)
    as there are still some things missing from the assembler.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a928d0ab467053b2d50e5dbe77170253acee44c9
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Dec 15 09:58:15 2020 -0800

    freedreno/ir3: Add some more disasm test vectors
    
    Various things that I noticed which were initially wrong with the xml
    based disasm.
    
    These were extracted from a collection of unique instructions extracted
    from deqp traces, which unfortunately looses the link back to the
    original test case.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2933d54992960b84ef8696b9d6de7cce91eec6b1
Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Dec 15 10:50:28 2020 -0800

    freedreno/ir3: Fix mova1 disasm
    
    Yet another mnemonic for mov
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3bd9aaf6ba3288cae74d19bc1265c9696390896
Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Dec 14 10:56:04 2020 -0800

    freedreno/ir3: Fix half-immed decoding issues
    
    For mov, half-float immeds are packed in 16b.  In other cases, the
    syntax for a half-immed is a bit different (ie. `h(1)`)
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f35ebd8a5435747b2a4ee58bbbfbc9cb29f03b8
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Sep 14 12:15:16 2020 +0200

    ir3: Support MOVMSK
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d36f36454fb79c990221e1d33e6fb4cccaff949
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Sep 16 16:44:08 2020 +0200

    ir3: Better rules for shared src copy propagation
    
    It turns out that the actual rule for when a source/dest can be shared
    is that it has to be cat1, cat2, or cat3. Allow this and silence
    warnings.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9804673fb6cd12134b90e52544da89b31f7886d
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Sep 10 12:14:24 2020 +0200

    ir3: Rename high registers to shared registers
    
    This more accurately reflects what they are.
    
    Signed-off-by: Rob Clark <robdclark at chromium.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>