Mesa (staging/20.3): util: add AMD CPU family enums and enable L3 cache pinning on Zen3

[GitLab Mirror]

Module: Mesa
Branch: staging/20.3
Commit: e9146fe6fb4053abbab3ebe1620fdfa15b2e2a43
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9146fe6fb4053abbab3ebe1620fdfa15b2e2a43

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Dec 24 05:43:25 2020 -0500

util: add AMD CPU family enums and enable L3 cache pinning on Zen3

Based on: https://en.wikichip.org/wiki/amd/cpuid

The only reason it's nominated as a fix is because Zen3 might underperform
because the CPU detection ignored it.

Fixes: 15fa2c5e359 - gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8225>
(cherry picked from commit e4fa7c440d273aad6cb9b9a6ee42a78810c9c2c2)

---

 .pick_status.json       |  2 +-
 src/util/u_cpu_detect.c | 15 ++++++++++++++-
 src/util/u_cpu_detect.h | 10 ++++++++++
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index e6605357ffb..f5386e3c237 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1255,7 +1255,7 @@
         "description": "util: add AMD CPU family enums and enable L3 cache pinning on Zen3",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "15fa2c5e359149a0b67b8572cd7dab87626b48ae"
     },
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index af3663a8bd6..025f2f30156 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -440,7 +440,8 @@ get_cpu_topology(void)
 
 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
    /* AMD Zen */
-   if (util_cpu_caps.x86_cpu_type == 0x17) {
+   if (util_cpu_caps.family >= CPU_AMD_ZEN1_ZEN2 &&
+       util_cpu_caps.family < CPU_AMD_LAST) {
       uint32_t regs[4];
 
       /* Query the L3 cache count. */
@@ -593,6 +594,18 @@ util_cpu_detect_once(void)
          if (util_cpu_caps.x86_cpu_type == 0xf)
              util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff);
 
+         switch (util_cpu_caps.x86_cpu_type) {
+         case 0x17:
+            util_cpu_caps.family = CPU_AMD_ZEN1_ZEN2;
+            break;
+         case 0x18:
+            util_cpu_caps.family = CPU_AMD_ZEN_HYGON;
+            break;
+         case 0x19:
+            util_cpu_caps.family = CPU_AMD_ZEN3;
+            break;
+         }
+
          /* general feature flags */
          util_cpu_caps.has_tsc    = (regs2[3] >>  4) & 1; /* 0x0000010 */
          util_cpu_caps.has_mmx    = (regs2[3] >> 23) & 1; /* 0x0800000 */
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index 2e47ee69af4..a76fd912910 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -44,10 +44,20 @@
 extern "C" {
 #endif
 
+enum cpu_family {
+   CPU_UNKNOWN,
+
+   CPU_AMD_ZEN1_ZEN2,
+   CPU_AMD_ZEN_HYGON,
+   CPU_AMD_ZEN3,
+   CPU_AMD_LAST,
+};
+
 typedef uint32_t util_affinity_mask[UTIL_MAX_CPUS / 32];
 
 struct util_cpu_caps {
    int nr_cpus;
+   enum cpu_family family;
 
    /* Feature flags */
    int x86_cpu_type;