Mesa (master): radv: vectorize shader I/O

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Module: Mesa
Branch: master
Commit: bfc777f83ed9a6ee1adaee383374bcc608e06988
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfc777f83ed9a6ee1adaee383374bcc608e06988

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Wed Jan  6 11:37:03 2021 +0000

radv: vectorize shader I/O

Fixes code size regressions after enabling TCS/TES for ACO.

fossil-db (Sienna):
Totals from 2588 (1.86% of 138791) affected shaders:
SGPRs: 109950 -> 108480 (-1.34%); split: -1.43%, +0.09%
VGPRs: 107764 -> 112060 (+3.99%); split: -0.03%, +4.02%
CodeSize: 5957760 -> 5321656 (-10.68%)
MaxWaves: 31718 -> 30358 (-4.29%); split: +0.03%, -4.32%
Instrs: 1116300 -> 1029000 (-7.82%)
Cycles: 4600344 -> 4251072 (-7.59%)
VMEM: 980024 -> 812978 (-17.05%); split: +1.14%, -18.18%
SMEM: 275458 -> 258227 (-6.26%); split: +2.34%, -8.60%
VClause: 42925 -> 30533 (-28.87%); split: -31.02%, +2.15%
SClause: 31554 -> 31362 (-0.61%); split: -1.79%, +1.18%
Branches: 15689 -> 15697 (+0.05%)
PreVGPRs: 80399 -> 83953 (+4.42%); split: -0.00%, +4.42%

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4202>

---

 src/amd/vulkan/radv_pipeline.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a4966722b91..678760487d0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2330,6 +2330,10 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders,
 		ordered_shaders[shader_count++] = shaders[MESA_SHADER_COMPUTE];
 	}
 
+	bool has_geom_tess = shaders[MESA_SHADER_GEOMETRY] || shaders[MESA_SHADER_TESS_CTRL];
+	bool merged_gs = shaders[MESA_SHADER_GEOMETRY] &&
+			 pipeline->device->physical_device->rad_info.chip_class >= GFX9;
+
 	if (!optimize_conservatively && shader_count > 1) {
 		unsigned first = ordered_shaders[shader_count - 1]->info.stage;
 		unsigned last = ordered_shaders[0]->info.stage;
@@ -2402,6 +2406,18 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders,
 		nir_compact_varyings(ordered_shaders[i],
 				     ordered_shaders[i - 1], true);
 
+		if (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_CTRL ||
+		    (ordered_shaders[i]->info.stage == MESA_SHADER_VERTEX && has_geom_tess) ||
+		    (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_EVAL && merged_gs)) {
+			nir_lower_io_to_vector(ordered_shaders[i], nir_var_shader_out);
+			nir_opt_combine_stores(ordered_shaders[i], nir_var_shader_out);
+		}
+		if (ordered_shaders[i - 1]->info.stage == MESA_SHADER_GEOMETRY ||
+		    ordered_shaders[i - 1]->info.stage == MESA_SHADER_TESS_CTRL ||
+		    ordered_shaders[i - 1]->info.stage == MESA_SHADER_TESS_EVAL) {
+			nir_lower_io_to_vector(ordered_shaders[i - 1], nir_var_shader_in);
+		}
+
 		if (progress) {
 			if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
 				ac_lower_indirect_derefs(ordered_shaders[i],