Mesa (master): ac/surface: initialize dcc_slice_size on GFX9+

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Module: Mesa
Branch: master
Commit: 7a3e6f5ac2a3773feb156d4e01bc17061baafb98
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a3e6f5ac2a3773feb156d4e01bc17061baafb98

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Jan  7 16:18:31 2021 +0100

ac/surface: initialize dcc_slice_size on GFX9+

Will be used by RADV to implement DCC layers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>

---

 src/amd/common/ac_surface.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index d9aef6e070d..fc29146d14a 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1844,6 +1844,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
          surf->u.gfx9.dcc_block_height = dout.compressBlkHeight;
          surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth;
          surf->dcc_size = dout.dccRamSize;
+         surf->dcc_slice_size = dout.dccRamSliceSize;
          surf->dcc_alignment = dout.dccRamBaseAlign;
          surf->num_dcc_levels = in->numMipLevels;