Mesa (master): radv: fix clearing DCC on GFX9

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: dbe845624bbbe8b34cf1cf85fe54869d71ca3528
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbe845624bbbe8b34cf1cf85fe54869d71ca3528

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Jan 12 13:55:54 2021 +0100

radv: fix clearing DCC on GFX9

dcc_slice_size is in DWORD on GFX9... Also, layers aren't supported
because they might be interleaved. Fix this by clearing the entire
DCC buffer.

Fixes: 5e8f6967b1d ("radv: add support for fast-clearing DCC layers on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8443>

---

 src/amd/vulkan/radv_meta_clear.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 66e9db40d04..decc5d4e18d 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1412,12 +1412,16 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 		uint32_t level = range->baseMipLevel + l;
 		uint64_t size;
 
-		if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+		if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
 			/* Mipmap levels aren't implemented. */
 			assert(level == 0);
 
 			offset += image->planes[0].surface.dcc_slice_size * range->baseArrayLayer;
 			size = image->planes[0].surface.dcc_slice_size * layer_count;
+		} else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
+			/* Mipmap levels and layers aren't implemented. */
+			assert(level == 0);
+			size = image->planes[0].surface.dcc_size;
 		} else {
 			const struct legacy_surf_level *surf_level =
 				&image->planes[0].surface.u.legacy.level[level];