Mesa (master): aco/ra: Remove always-false conditions

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Jan 13 18:31:39 UTC 2021


Module: Mesa
Branch: master
Commit: 689ce1f39d32bec64aeb2354ff67a242c833b59c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=689ce1f39d32bec64aeb2354ff67a242c833b59c

Author: Tony Wasserka <tony.wasserka at gmx.de>
Date:   Wed Oct 28 23:38:20 2020 +0100

aco/ra: Remove always-false conditions

All code paths that set "found" to true either break or return before the
loop header is reached again, so the checks are unnecessary.

Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>

---

 src/amd/compiler/aco_register_allocation.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 050a3acc607..6bc8e07901b 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -740,7 +740,7 @@ std::pair<PhysReg, bool> get_reg_simple(ra_ctx& ctx,
 
    bool found = false;
    PhysRegInterval reg_win = { bounds.lo(), size };
-   while (!found && reg_win.hi() <= bounds.hi()) {
+   while (reg_win.hi() <= bounds.hi()) {
       if (reg_file[reg_win.lo()] != 0) {
          reg_win += stride;
          continue;
@@ -1046,7 +1046,7 @@ std::pair<PhysReg, bool> get_reg_impl(ra_ctx& ctx,
       unsigned last_var = 0;
       bool found = true;
       bool aligned = rc == RegClass::v4 && reg_win.lo() % 4 == 0;
-      for (unsigned j = reg_win.lo(); found && j < reg_win.hi(); j++) {
+      for (unsigned j = reg_win.lo(); j < reg_win.hi(); j++) {
          /* dead operands effectively reduce the number of estimated moves */
          if (is_killed_operand[j & 0xFF]) {
             if (remaining_op_moves) {
@@ -1176,7 +1176,7 @@ bool get_reg_specified(ra_ctx& ctx,
    uint32_t reg_lo = reg.reg();
    uint32_t reg_hi = reg + (size - 1);
 
-   if (reg_lo < lb || reg_hi >= ub || reg_lo > reg_hi)
+   if (reg_lo < lb || reg_hi >= ub)
       return false;
 
    if (rc.is_subdword()) {



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