Mesa (master): freedreno/ir3: Add some new "logical" opcodes

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Module: Mesa
Branch: master
Commit: 6309c9313b194cb269da54e3553ddb0c001eed3a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6309c9313b194cb269da54e3553ddb0c001eed3a

Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Dec 30 11:51:23 2020 -0800

freedreno/ir3: Add some new "logical" opcodes

Once we switch over to the xml based ir3 ISA definition, the opcodes
will be decoupled from instruction encoding.  Which will let us better
handle cases where a single "opcode" (from instruction encoding stand-
point) means different things on different generations.  And also cases
like the different variations of `b`ranch instructions, which share a
single hw "opcode" plus a separate "brtype" field.  When we start using
these in ir3, we'd like to treat them as separate instructions and not
have to care about the details of how they are encoded.

For now, these are only used internally within the new xml generated
instruction encoding, but once the existing "packed struct" encoding/
decoding is replace, we'll update ir3 to start using the new opcode
enums directly (except for the `mov` variants).

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>

---

 src/freedreno/ir3/instr-a3xx.h | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 2eaf73a18b3..36ae363877e 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -81,10 +81,26 @@ typedef enum {
 	OPC_PREDF           = _OPC(0, 30),   /* predicated false */
 	OPC_PREDE           = _OPC(0, 31),   /* predicated end */
 
+	/* Logical opcodes for different branch instruction variations: */
+	OPC_BR              = _OPC(0, 40),
+	OPC_BRAO            = _OPC(0, 41),
+	OPC_BRAA            = _OPC(0, 42),
+	OPC_BRAC            = _OPC(0, 43),
+	OPC_BANY            = _OPC(0, 44),
+	OPC_BALL            = _OPC(0, 45),
+	OPC_BRAX            = _OPC(0, 46),
+
 	/* category 1: */
 	OPC_MOV             = _OPC(1, 0),
 	OPC_MOVMSK          = _OPC(1, 3),
 
+	/* Logical opcodes for different variants of mov: */
+	OPC_MOV_IMMED       = _OPC(1, 40),
+	OPC_MOV_CONST       = _OPC(1, 41),
+	OPC_MOV_GPR         = _OPC(1, 42),
+	OPC_MOV_RELGPR      = _OPC(1, 43),
+	OPC_MOV_RELCONST    = _OPC(1, 44),
+
 	/* category 2: */
 	OPC_ADD_F           = _OPC(2, 0),
 	OPC_MIN_F           = _OPC(2, 1),
@@ -244,6 +260,24 @@ typedef enum {
 	OPC_GETSPID         = _OPC(6, 36), /* SP ID */
 	OPC_GETWID          = _OPC(6, 37), /* wavefront ID */
 
+	/* Logical opcodes for things that differ in a6xx+ */
+	OPC_STC             = _OPC(6, 40),
+	OPC_RESINFO_B       = _OPC(6, 41),
+	OPC_LDIB_B          = _OPC(6, 42),
+	OPC_STIB_B          = _OPC(6, 43),
+
+	/* Logical opcodes for different atomic instruction variations: */
+	OPC_ATOMIC_B_ADD      = _OPC(6, 44),
+	OPC_ATOMIC_B_SUB      = _OPC(6, 45),
+	OPC_ATOMIC_B_XCHG     = _OPC(6, 46),
+	OPC_ATOMIC_B_INC      = _OPC(6, 47),
+	OPC_ATOMIC_B_DEC      = _OPC(6, 48),
+	OPC_ATOMIC_B_CMPXCHG  = _OPC(6, 49),
+	OPC_ATOMIC_B_MIN      = _OPC(6, 50),
+	OPC_ATOMIC_B_MAX      = _OPC(6, 51),
+	OPC_ATOMIC_B_AND      = _OPC(6, 52),
+	OPC_ATOMIC_B_OR       = _OPC(6, 53),
+	OPC_ATOMIC_B_XOR      = _OPC(6, 54),
 
 	/* category 7: */
 	OPC_BAR             = _OPC(7, 0),