Mesa (master): freedreno/ir3: Fix ldg decoding/parsing

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Jan 13 18:53:08 UTC 2021


Module: Mesa
Branch: master
Commit: e1f8aaf9d2a3743cc6f9dc50cbab19db5833bd75
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1f8aaf9d2a3743cc6f9dc50cbab19db5833bd75

Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Jan  4 12:47:36 2021 -0800

freedreno/ir3: Fix ldg decoding/parsing

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>

---

 src/freedreno/ir3/tests/disasm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c
index c35f96b7005..4f4633c1059 100644
--- a/src/freedreno/ir3/tests/disasm.c
+++ b/src/freedreno/ir3/tests/disasm.c
@@ -154,6 +154,11 @@ static const struct test {
 	INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
 	INSTR_6XX(c0060003_0180c269, "ldg.u32 r0.w, g[r0.w+308], 1"),
 
+	INSTR_6XX(c0020011_04c08023, "ldg.f32 r4.y, g[r0.z+r4.y], 4"), /* ldg.a.f32 r4.y, g[r0.z+(r4.y<<2)], 4 */
+	INSTR_6XX(c0060006_01c18017, "ldg.u32 r1.z, g[r1.z+r2.w], 1"), /* ldg.a.u32 r1.z, g[r1.z+(r2.w<<2)], 1 */
+	INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
+	INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
+
 	/* TODO: We don't support disasm of stc yet and produce a stgb instead
 	 * (same as their disasm does for other families.  They're used as part
 	 * uniforms setup, followed by a shpe and then a load of the constant that



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