Mesa (staging/21.0): radeonsi: invalidate compute sgprs in si_rebind_buffer
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Thu Jan 14 18:44:09 UTC 2021
Module: Mesa
Branch: staging/21.0
Commit: 074631dd6781ad576461d67caa9e457b5e3d2d7a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=074631dd6781ad576461d67caa9e457b5e3d2d7a
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Mon Jan 11 20:40:09 2021 +0100
radeonsi: invalidate compute sgprs in si_rebind_buffer
If we don't tag compute sgpr as dirty they will point to the
ol buffer location.
This fixes arb_compute_shader-dlist with mcbp enabled.
Fixes: 85a6bcca615 ("radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute")
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
(cherry picked from commit 17f8e56c96ca6cfafa90c87564441b4fb7fa1b23)
---
.pick_status.json | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 22 ++++++++++++++++------
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 055ec9dc322..074a959e96f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -40,7 +40,7 @@
"description": "radeonsi: invalidate compute sgprs in si_rebind_buffer",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "85a6bcca615f9aae1ffd2a1e790ee5d980e7cc43"
},
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 4b9aeaff4d5..21f9ae4b146 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1482,11 +1482,12 @@ void si_update_needs_color_decompress_masks(struct si_context *sctx)
/* Reset descriptors of buffer resources after \p buf has been invalidated.
* If buf == NULL, reset all descriptors.
*/
-static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
+static bool si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
unsigned descriptors_idx, uint64_t slot_mask,
struct pipe_resource *buf, enum radeon_bo_priority priority)
{
struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
+ bool noop = true;
uint64_t mask = buffers->enabled_mask & slot_mask;
while (mask) {
@@ -1501,8 +1502,10 @@ static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_
sctx, si_resource(buffer),
buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
priority, true);
+ noop = false;
}
}
+ return !noop;
}
/* Update all buffer bindings where the buffer is bound, including
@@ -1577,11 +1580,15 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
}
if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
- for (shader = 0; shader < SI_NUM_SHADERS; shader++)
- si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
- si_const_and_shader_buffer_descriptors_idx(shader),
- u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
- sctx->const_and_shader_buffers[shader].priority);
+ for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+ if (si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
+ si_const_and_shader_buffer_descriptors_idx(shader),
+ u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
+ sctx->const_and_shader_buffers[shader].priority) &&
+ shader == PIPE_SHADER_COMPUTE) {
+ sctx->compute_shaderbuf_sgprs_dirty = true;
+ }
+ }
}
if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
@@ -1633,6 +1640,9 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER, true);
+
+ if (shader == PIPE_SHADER_COMPUTE)
+ sctx->compute_image_sgprs_dirty = true;
}
}
}
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