Mesa (master): turnip: make GS use correct varyings size from previous stage

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Module: Mesa
Branch: master
Commit: cea4d85093af807ea0f84d505929766918452892
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cea4d85093af807ea0f84d505929766918452892

Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date:   Thu Jan 14 19:13:19 2021 +0200

turnip: make GS use correct varyings size from previous stage

Fixes:
 dEQP-VK.tessellation.invariance.primitive_set.triangles_fractional_even_spacing_ccw
 dEQP-VK.tessellation.invariance.outer_edge_division.triangles_fractional_even_spacing
 dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_fractional_odd_spacing_cw
 dEQP-VK.tessellation.invariance.outer_edge_symmetry.quads_fractional_odd_spacing_ccw
 dEQP-VK.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_cw
 dEQP-VK.tessellation.invariance.outer_edge_index_independence.triangles_equal_spacing_ccw
 dEQP-VK.tessellation.invariance.outer_edge_index_independence.triangles_fractional_even_spacing_cw
 dEQP-VK.tessellation.invariance.inner_triangle_set.triangles_equal_spacing

Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8497>

---

 .gitlab-ci/deqp-freedreno-a630-fails.txt | 8 --------
 src/freedreno/vulkan/tu_pipeline.c       | 6 ++++--
 2 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/.gitlab-ci/deqp-freedreno-a630-fails.txt b/.gitlab-ci/deqp-freedreno-a630-fails.txt
index b92a6a1bf30..cf71d326ed2 100644
--- a/.gitlab-ci/deqp-freedreno-a630-fails.txt
+++ b/.gitlab-ci/deqp-freedreno-a630-fails.txt
@@ -40,15 +40,7 @@ dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_too_small_tesse,
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_tesse,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_tesse,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_tesse,Fail
-dEQP-VK.tessellation.invariance.inner_triangle_set.triangles_equal_spacing,Fail
-dEQP-VK.tessellation.invariance.outer_edge_division.triangles_fractional_even_spacing,Fail
-dEQP-VK.tessellation.invariance.outer_edge_index_independence.triangles_equal_spacing_ccw,Fail
-dEQP-VK.tessellation.invariance.outer_edge_index_independence.triangles_fractional_even_spacing_cw,Fail
 dEQP-VK.tessellation.invariance.outer_edge_index_independence.quads_fractional_even_spacing_ccw,Fail
-dEQP-VK.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_cw,Fail
-dEQP-VK.tessellation.invariance.outer_edge_symmetry.quads_fractional_odd_spacing_ccw,Fail
-dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_fractional_odd_spacing_cw,Fail
 dEQP-VK.tessellation.invariance.outer_triangle_set.quads_fractional_odd_spacing,Fail
 dEQP-VK.tessellation.invariance.primitive_set.isolines_fractional_odd_spacing_ccw,Fail
 dEQP-VK.tessellation.invariance.primitive_set.quads_fractional_odd_spacing_cw,Fail
-dEQP-VK.tessellation.invariance.primitive_set.triangles_fractional_even_spacing_ccw,Fail
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index b7e9d2d20aa..acc6c12044a 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1055,6 +1055,8 @@ tu6_emit_vpc(struct tu_cs *cs,
 
    if (gs) {
       uint32_t vertices_out, invocations, output, vec4_size;
+      uint32_t prev_stage_output_size = ds ? ds->output_size : vs->output_size;
+
       /* this detects the tu_clear_blit path, which doesn't set ->nir */
       if (gs->shader->nir) {
          if (hs) {
@@ -1067,7 +1069,7 @@ tu6_emit_vpc(struct tu_cs *cs,
          invocations = gs->shader->nir->info.gs.invocations - 1;
          /* Size of per-primitive alloction in ldlw memory in vec4s. */
          vec4_size = gs->shader->nir->info.gs.vertices_in *
-                     DIV_ROUND_UP(vs->output_size, 4);
+                     DIV_ROUND_UP(prev_stage_output_size, 4);
       } else {
          vertices_out = 3;
          output = TESS_CW_TRIS;
@@ -1091,7 +1093,7 @@ tu6_emit_vpc(struct tu_cs *cs,
       tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
 
       tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
-      tu_cs_emit(cs, vs->output_size);
+      tu_cs_emit(cs, prev_stage_output_size);
    }
 }