Mesa (staging/21.0): r600/sfn: fix use of b32all/and

[GitLab Mirror]

Module: Mesa
Branch: staging/21.0
Commit: e63774d093b79b3ca86e37660b2f3c4104ec9b8a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e63774d093b79b3ca86e37660b2f3c4104ec9b8a

Author: Gert Wollny <gert.wollny at collabora.com>
Date:   Sun Jan 17 17:55:56 2021 +0100

r600/sfn: fix use of b32all/and

Fixes: f79b7fcf7c7f5db626efdb63f27e8bc64d0aed77
       r600/sfn: use 32 bit bools

Signed-off-by: Gert Wollny <gert.wollny at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8563>
(cherry picked from commit 198c3acacf43389822c1cafd436eabd7127a199d)

---

 .pick_status.json                                  |  2 +-
 .../drivers/r600/sfn/sfn_emitaluinstruction.cpp    | 27 ++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 0ca30c7736f..7d12a1e9faa 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -211,7 +211,7 @@
         "description": "r600/sfn: fix use of b32all/and",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "f79b7fcf7c7f5db626efdb63f27e8bc64d0aed77"
     },
diff --git a/src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.cpp b/src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.cpp
index 1a29ea57b8c..413b2218dd5 100644
--- a/src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.cpp
@@ -165,6 +165,21 @@ bool EmitAluInstruction::do_emit(nir_instr* ir)
    case nir_op_ball_fequal3: return emit_any_all_fcomp(instr, op2_sete, 3, true);
    case nir_op_ball_fequal4: return emit_any_all_fcomp(instr, op2_sete, 4, true);
 
+   case nir_op_b32any_inequal2: return emit_any_all_icomp(instr, op2_setne_int, 2, false);
+   case nir_op_b32any_inequal3: return emit_any_all_icomp(instr, op2_setne_int, 3, false);
+   case nir_op_b32any_inequal4: return emit_any_all_icomp(instr, op2_setne_int, 4, false);
+
+   case nir_op_b32all_iequal2: return emit_any_all_icomp(instr, op2_sete_int, 2, true);
+   case nir_op_b32all_iequal3: return emit_any_all_icomp(instr, op2_sete_int, 3, true);
+   case nir_op_b32all_iequal4: return emit_any_all_icomp(instr, op2_sete_int, 4, true);
+
+   case nir_op_b32any_fnequal2: return emit_any_all_fcomp2(instr, op2_setne_dx10, false);
+   case nir_op_b32any_fnequal3: return emit_any_all_fcomp(instr, op2_setne, 3, false);
+   case nir_op_b32any_fnequal4: return emit_any_all_fcomp(instr, op2_setne, 4, false);
+
+   case nir_op_b32all_fequal2: return emit_any_all_fcomp2(instr, op2_sete_dx10, true);
+   case nir_op_b32all_fequal3: return emit_any_all_fcomp(instr, op2_sete, 3, true);
+   case nir_op_b32all_fequal4: return emit_any_all_fcomp(instr, op2_sete, 4, true);
 
    case nir_op_ffma: return emit_alu_op3(instr, op3_muladd_ieee);
    case nir_op_b32csel: return emit_alu_op3(instr, op3_cnde,  {0, 2, 1});
@@ -232,6 +247,10 @@ unsigned EmitAluInstruction::num_src_comp(const nir_alu_instr& instr)
    case nir_op_ball_iequal2:
    case nir_op_bany_fnequal2:
    case nir_op_ball_fequal2:
+   case nir_op_b32any_inequal2:
+   case nir_op_b32all_iequal2:
+   case nir_op_b32any_fnequal2:
+   case nir_op_b32all_fequal2:
    case nir_op_unpack_64_2x32_split_y:
       return 2;
 
@@ -240,6 +259,10 @@ unsigned EmitAluInstruction::num_src_comp(const nir_alu_instr& instr)
    case nir_op_ball_iequal3:
    case nir_op_bany_fnequal3:
    case nir_op_ball_fequal3:
+   case nir_op_b32any_inequal3:
+   case nir_op_b32all_iequal3:
+   case nir_op_b32any_fnequal3:
+   case nir_op_b32all_fequal3:
       return 3;
 
    case nir_op_fdot4:
@@ -248,6 +271,10 @@ unsigned EmitAluInstruction::num_src_comp(const nir_alu_instr& instr)
    case nir_op_ball_iequal4:
    case nir_op_bany_fnequal4:
    case nir_op_ball_fequal4:
+   case nir_op_b32any_inequal4:
+   case nir_op_b32all_iequal4:
+   case nir_op_b32any_fnequal4:
+   case nir_op_b32all_fequal4:
       return 4;
 
    case nir_op_vec2: