Mesa (master): docs/freedreno: Fix a few typos

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Module: Mesa
Branch: master
Commit: facd34431b74b9790d3769fd643356483db184e9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=facd34431b74b9790d3769fd643356483db184e9

Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jan 20 14:40:42 2021 -0500

docs/freedreno: Fix a few typos

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8599>

---

 docs/drivers/freedreno/ir3-notes.rst | 4 ++--
 docs/drivers/freedreno/isaspec.rst   | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/docs/drivers/freedreno/ir3-notes.rst b/docs/drivers/freedreno/ir3-notes.rst
index bded59e0e93..ef7ceb0e144 100644
--- a/docs/drivers/freedreno/ir3-notes.rst
+++ b/docs/drivers/freedreno/ir3-notes.rst
@@ -409,7 +409,7 @@ In the grouping pass, instructions which need to be grouped (for ``fanin``\s, et
 Depth
 ~~~~~
 
-In the depth pass, a depth is calculated for each instruction node within it's basic block.  The depth is the sum of the required cycles (delay slots needed between two instructions plus one) of each instruction plus the max depth of any of it's source instructions.  (meta_ instructions don't add to the depth).  As an instruction's depth is calculated, it is inserted into a per block list sorted by deepest instruction.  Unreachable instructions and inputs are marked.
+In the depth pass, a depth is calculated for each instruction node within its basic block.  The depth is the sum of the required cycles (delay slots needed between two instructions plus one) of each instruction plus the max depth of any of its source instructions.  (meta_ instructions don't add to the depth).  As an instruction's depth is calculated, it is inserted into a per block list sorted by deepest instruction.  Unreachable instructions and inputs are marked.
 
     TODO: we should probably calculate both hard and soft depths (?) to
     try to coax additional instructions to fit in places where we need
@@ -420,7 +420,7 @@ In the depth pass, a depth is calculated for each instruction node within it's b
 Scheduling
 ~~~~~~~~~~
 
-After the grouping_ pass, there are no more instructions to insert or remove.  Start scheduling each basic block from the deepest node in the depth sorted list created by the depth_ pass, recursively trying to schedule each instruction after it's source instructions plus delay slots.  Insert ``nop``\s as required.
+After the grouping_ pass, there are no more instructions to insert or remove.  Start scheduling each basic block from the deepest node in the depth sorted list created by the depth_ pass, recursively trying to schedule each instruction after its source instructions plus delay slots.  Insert ``nop``\s as required.
 
 .. _`register assignment`:
 
diff --git a/docs/drivers/freedreno/isaspec.rst b/docs/drivers/freedreno/isaspec.rst
index df67c71effb..a1dffe9e0ee 100644
--- a/docs/drivers/freedreno/isaspec.rst
+++ b/docs/drivers/freedreno/isaspec.rst
@@ -9,8 +9,8 @@ underlying instruction encoding to simplify dealing with instruction
 encoding differences between generations of GPU.
 
 Benefits of a formal ISA description, compared to hand-coded assemblers
-and disassemblers, include easier detection of new bit combintions that
-were not seen before in previous generations due to more rigerous
+and disassemblers, include easier detection of new bit combinations that
+were not seen before in previous generations due to more rigorous
 description of bits that are expect to be '0' or '1' or 'x' (dontcare)
 and verification that different encodings don't have conflicting bits
 (ie. that the specification cannot result in more than one valid
@@ -276,4 +276,4 @@ with the specified prefix prepended to uppercase'd leaf node name.  Ie. in
 this case, "add.f" becomes ``OPC_ADD_F``.
 
 Individual ``<map>`` elements teach the encoder how to map from the encode
-source to fields in the encoded instruction.
\ No newline at end of file
+source to fields in the encoded instruction.