Mesa (master): radeonsi: add si_get_user_data_base selecting user data registers
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Jan 20 22:13:28 UTC 2021
Module: Mesa
Branch: master
Commit: e8ccb6f0f39808306c1160d783a144212ef72cd6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8ccb6f0f39808306c1160d783a144212ef72cd6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jan 9 06:42:55 2021 -0500
radeonsi: add si_get_user_data_base selecting user data registers
This will be used in templated si_draw_vbo in place of sh_base.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8600>
---
src/gallium/drivers/radeonsi/si_build_pm4.h | 67 +++++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_descriptors.c | 71 ++++++++-------------------
2 files changed, 88 insertions(+), 50 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 0294c455fb2..3ccf3529d56 100644
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -283,4 +283,71 @@ static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned
}
}
+/* This should be evaluated at compile time if all parameters are constants. */
+static ALWAYS_INLINE unsigned
+si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess,
+ enum si_has_gs has_gs, enum si_has_ngg ngg,
+ enum pipe_shader_type shader)
+{
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ /* VS can be bound as VS, ES, or LS. */
+ if (has_tess) {
+ if (chip_class >= GFX10) {
+ return R_00B430_SPI_SHADER_USER_DATA_HS_0;
+ } else if (chip_class == GFX9) {
+ return R_00B430_SPI_SHADER_USER_DATA_LS_0;
+ } else {
+ return R_00B530_SPI_SHADER_USER_DATA_LS_0;
+ }
+ } else if (chip_class >= GFX10) {
+ if (ngg || has_gs) {
+ return R_00B230_SPI_SHADER_USER_DATA_GS_0;
+ } else {
+ return R_00B130_SPI_SHADER_USER_DATA_VS_0;
+ }
+ } else if (has_gs) {
+ return R_00B330_SPI_SHADER_USER_DATA_ES_0;
+ } else {
+ return R_00B130_SPI_SHADER_USER_DATA_VS_0;
+ }
+
+ case PIPE_SHADER_TESS_CTRL:
+ if (chip_class == GFX9) {
+ return R_00B430_SPI_SHADER_USER_DATA_LS_0;
+ } else {
+ return R_00B430_SPI_SHADER_USER_DATA_HS_0;
+ }
+
+ case PIPE_SHADER_TESS_EVAL:
+ /* TES can be bound as ES, VS, or not bound. */
+ if (has_tess) {
+ if (chip_class >= GFX10) {
+ if (ngg || has_gs) {
+ return R_00B230_SPI_SHADER_USER_DATA_GS_0;
+ } else {
+ return R_00B130_SPI_SHADER_USER_DATA_VS_0;
+ }
+ } else if (has_gs) {
+ return R_00B330_SPI_SHADER_USER_DATA_ES_0;
+ } else {
+ return R_00B130_SPI_SHADER_USER_DATA_VS_0;
+ }
+ } else {
+ return 0;
+ }
+
+ case PIPE_SHADER_GEOMETRY:
+ if (chip_class == GFX9) {
+ return R_00B330_SPI_SHADER_USER_DATA_ES_0;
+ } else {
+ return R_00B230_SPI_SHADER_USER_DATA_GS_0;
+ }
+
+ default:
+ assert(0);
+ return 0;
+ }
+}
+
#endif
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index bf01803ebac..1fbbfd40ff3 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1915,43 +1915,19 @@ static void si_set_user_data_base(struct si_context *sctx, unsigned shader, uint
*/
void si_shader_change_notify(struct si_context *sctx)
{
- /* VS can be bound as VS, ES, or LS. */
- if (sctx->tes_shader.cso) {
- if (sctx->chip_class >= GFX10) {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0);
- } else if (sctx->chip_class == GFX9) {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B530_SPI_SHADER_USER_DATA_LS_0);
- }
- } else if (sctx->chip_class >= GFX10) {
- if (sctx->ngg || sctx->gs_shader.cso) {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- }
- } else if (sctx->gs_shader.cso) {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- }
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ si_get_user_data_base(sctx->chip_class,
+ sctx->tes_shader.cso ? TESS_ON : TESS_OFF,
+ sctx->gs_shader.cso ? GS_ON : GS_OFF,
+ sctx->ngg ? NGG_ON : NGG_OFF,
+ PIPE_SHADER_VERTEX));
- /* TES can be bound as ES, VS, or not bound. */
- if (sctx->tes_shader.cso) {
- if (sctx->chip_class >= GFX10) {
- if (sctx->ngg || sctx->gs_shader.cso) {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B230_SPI_SHADER_USER_DATA_GS_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- }
- } else if (sctx->gs_shader.cso) {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B330_SPI_SHADER_USER_DATA_ES_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- }
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
- }
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
+ si_get_user_data_base(sctx->chip_class,
+ sctx->tes_shader.cso ? TESS_ON : TESS_OFF,
+ sctx->gs_shader.cso ? GS_ON : GS_OFF,
+ sctx->ngg ? NGG_ON : NGG_OFF,
+ PIPE_SHADER_TESS_EVAL));
}
static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset,
@@ -2631,20 +2607,15 @@ void si_init_all_descriptors(struct si_context *sctx)
sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers;
/* Set default and immutable mappings. */
- if (sctx->ngg) {
- assert(sctx->chip_class >= GFX10);
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
- }
-
- if (sctx->chip_class == GFX9) {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_LS_0);
- si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B330_SPI_SHADER_USER_DATA_ES_0);
- } else {
- si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
- si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
- }
+ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
+ si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF,
+ sctx->ngg, PIPE_SHADER_VERTEX));
+ si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL,
+ si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF,
+ NGG_OFF, PIPE_SHADER_TESS_CTRL));
+ si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY,
+ si_get_user_data_base(sctx->chip_class, TESS_OFF, GS_OFF,
+ NGG_OFF, PIPE_SHADER_GEOMETRY));
si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
}
More information about the mesa-commit
mailing list