Mesa (master): radeonsi: evaluate si_get_vs in si_draw_vbo at compile time

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 888a45a36217f0ccac8d6afd5937dc3a5f3f5828
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=888a45a36217f0ccac8d6afd5937dc3a5f3f5828

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Jan  9 07:31:49 2021 -0500

radeonsi: evaluate si_get_vs in si_draw_vbo at compile time

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8600>

---

 src/gallium/drivers/radeonsi/si_pipe.h         | 14 +++++++++++---
 src/gallium/drivers/radeonsi/si_state_draw.cpp | 12 ++++++------
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 1a2a16f4ec0..e00f9a1af3d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1678,16 +1678,24 @@ static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *a
    si_set_atom_dirty(sctx, atom, true);
 }
 
-static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
+/* This should be evaluated at compile time if all parameters except sctx are constants. */
+static ALWAYS_INLINE struct si_shader_ctx_state *
+si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
 {
-   if (sctx->gs_shader.cso)
+   if (has_gs)
       return &sctx->gs_shader;
-   if (sctx->tes_shader.cso)
+   if (has_tess)
       return &sctx->tes_shader;
 
    return &sctx->vs_shader;
 }
 
+static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
+{
+   return si_get_vs_inline(sctx, sctx->tes_shader.cso ? TESS_ON : TESS_OFF,
+                           sctx->gs_shader.cso ? GS_ON : GS_OFF);
+}
+
 static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
 {
    struct si_shader_ctx_state *vs = si_get_vs(sctx);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index 179f8f826e8..d1a2ff67cef 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -730,7 +730,7 @@ static unsigned si_conv_prim_to_gs_out(unsigned mode)
 }
 
 /* rast_prim is the primitive type after GS. */
-template<chip_class GFX_VERSION, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE
+template<chip_class GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE
 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
 {
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
@@ -762,7 +762,7 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
       sctx->context_roll = true;
 
    if (NGG) {
-      struct si_shader *hw_vs = si_get_vs(sctx)->current;
+      struct si_shader *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current;
 
       if (hw_vs->uses_vs_state_provoking_vertex) {
          unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
@@ -874,7 +874,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
                    S_03096C_VERT_GRP_SIZE(0) |
                    S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
       } else {
-         ge_cntl = si_get_vs(sctx)->current->ge_cntl;
+         ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl;
       }
    } else {
       unsigned primgroup_size;
@@ -1478,7 +1478,7 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
 {
    unsigned num_patches = 0;
 
-   si_emit_rasterizer_prim_state<GFX_VERSION, HAS_GS, NGG>(sctx);
+   si_emit_rasterizer_prim_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx);
    if (HAS_TESS)
       si_emit_derived_tess_state(sctx, info->vertices_per_patch, &num_patches);
 
@@ -1898,7 +1898,7 @@ static void si_draw_vbo(struct pipe_context *ctx,
    if (GFX_VERSION >= GFX10) {
       struct si_shader_selector *hw_vs;
       if (NGG && !dispatch_prim_discard_cs && rast_prim == PIPE_PRIM_TRIANGLES &&
-          (hw_vs = si_get_vs(sctx)->cso) &&
+          (hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->cso) &&
           (total_direct_count > hw_vs->ngg_cull_vert_threshold ||
            (!index_size &&
             total_direct_count > hw_vs->ngg_cull_nonindexed_fast_launch_vert_threshold &&
@@ -1971,7 +1971,7 @@ static void si_draw_vbo(struct pipe_context *ctx,
        * This is the setting that is used by the draw.
        */
       if (GFX_VERSION >= GFX10) {
-         uint8_t ngg_culling = si_get_vs(sctx)->current->key.opt.ngg_culling;
+         uint8_t ngg_culling = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->key.opt.ngg_culling;
          if (GFX_VERSION == GFX10 &&
              !(old_ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL) &&
              ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)