Mesa (master): radv: don't vectorize shift operations

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Module: Mesa
Branch: master
Commit: e10779a9f0da62b3968f48ae9d8c9d5275c7aac2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e10779a9f0da62b3968f48ae9d8c9d5275c7aac2

Author: Daniel Schürmann <daniel at schuermann.dev>
Date:   Thu Jan 21 12:13:39 2021 +0100

radv: don't vectorize shift operations

Currently, these cannot be vectorized as in NIR
shift operands are 32bit while for 16bit-vectorization
they need to be 16bit.

No fossildb changes.

Fixes: fcd2ef23e5f1d50008166168e772815c0213e37c ('radv: vectorize 16bit instructions')

Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8612>

---

 src/amd/vulkan/radv_pipeline.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a910cfc16b5..db3c36850e3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3181,10 +3181,10 @@ opt_vectorize_callback(const nir_instr *instr, void *_)
    case nir_op_imax:
    case nir_op_umin:
    case nir_op_umax:
-   case nir_op_ishl:
-   case nir_op_ishr:
-   case nir_op_ushr:
       return true;
+   case nir_op_ishl: /* TODO: in NIR, these have 32bit shift operands */
+   case nir_op_ishr: /* while Radeon needs 16bit operands when vectorized */
+   case nir_op_ushr:
    default:
       return false;
    }