Mesa (master): intel/compiler: Move brw_reg_type_for_bit_size to brw_reg_type.h

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: e797daba538e605b6b94cb28c922384cef9ef014
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e797daba538e605b6b94cb28c922384cef9ef014

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Mon Oct 26 12:22:20 2020 -0500

intel/compiler: Move brw_reg_type_for_bit_size to brw_reg_type.h

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7329>

---

 src/intel/compiler/brw_fs_nir.cpp | 65 ---------------------------------------
 src/intel/compiler/brw_reg_type.h | 60 ++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+), 65 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 19ead829755..ff22266af91 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -293,71 +293,6 @@ fs_visitor::nir_emit_system_values()
       emit_system_values_block(block, this);
 }
 
-/*
- * Returns a type based on a reference_type (word, float, half-float) and a
- * given bit_size.
- *
- * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
- *
- * @FIXME: 64-bit return types are always DF on integer types to maintain
- * compability with uses of DF previously to the introduction of int64
- * support.
- */
-static brw_reg_type
-brw_reg_type_from_bit_size(const unsigned bit_size,
-                           const brw_reg_type reference_type)
-{
-   switch(reference_type) {
-   case BRW_REGISTER_TYPE_HF:
-   case BRW_REGISTER_TYPE_F:
-   case BRW_REGISTER_TYPE_DF:
-      switch(bit_size) {
-      case 16:
-         return BRW_REGISTER_TYPE_HF;
-      case 32:
-         return BRW_REGISTER_TYPE_F;
-      case 64:
-         return BRW_REGISTER_TYPE_DF;
-      default:
-         unreachable("Invalid bit size");
-      }
-   case BRW_REGISTER_TYPE_B:
-   case BRW_REGISTER_TYPE_W:
-   case BRW_REGISTER_TYPE_D:
-   case BRW_REGISTER_TYPE_Q:
-      switch(bit_size) {
-      case 8:
-         return BRW_REGISTER_TYPE_B;
-      case 16:
-         return BRW_REGISTER_TYPE_W;
-      case 32:
-         return BRW_REGISTER_TYPE_D;
-      case 64:
-         return BRW_REGISTER_TYPE_Q;
-      default:
-         unreachable("Invalid bit size");
-      }
-   case BRW_REGISTER_TYPE_UB:
-   case BRW_REGISTER_TYPE_UW:
-   case BRW_REGISTER_TYPE_UD:
-   case BRW_REGISTER_TYPE_UQ:
-      switch(bit_size) {
-      case 8:
-         return BRW_REGISTER_TYPE_UB;
-      case 16:
-         return BRW_REGISTER_TYPE_UW;
-      case 32:
-         return BRW_REGISTER_TYPE_UD;
-      case 64:
-         return BRW_REGISTER_TYPE_UQ;
-      default:
-         unreachable("Invalid bit size");
-      }
-   default:
-      unreachable("Unknown type");
-   }
-}
-
 void
 fs_visitor::nir_emit_impl(nir_function_impl *impl)
 {
diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h
index a17c93ee90e..9263a987060 100644
--- a/src/intel/compiler/brw_reg_type.h
+++ b/src/intel/compiler/brw_reg_type.h
@@ -100,6 +100,66 @@ brw_reg_type_is_integer(enum brw_reg_type type)
    }
 }
 
+/*
+ * Returns a type based on a reference_type (word, float, half-float) and a
+ * given bit_size.
+ */
+static inline enum brw_reg_type
+brw_reg_type_from_bit_size(unsigned bit_size,
+                           enum brw_reg_type reference_type)
+{
+   switch(reference_type) {
+   case BRW_REGISTER_TYPE_HF:
+   case BRW_REGISTER_TYPE_F:
+   case BRW_REGISTER_TYPE_DF:
+      switch(bit_size) {
+      case 16:
+         return BRW_REGISTER_TYPE_HF;
+      case 32:
+         return BRW_REGISTER_TYPE_F;
+      case 64:
+         return BRW_REGISTER_TYPE_DF;
+      default:
+         unreachable("Invalid bit size");
+      }
+   case BRW_REGISTER_TYPE_B:
+   case BRW_REGISTER_TYPE_W:
+   case BRW_REGISTER_TYPE_D:
+   case BRW_REGISTER_TYPE_Q:
+      switch(bit_size) {
+      case 8:
+         return BRW_REGISTER_TYPE_B;
+      case 16:
+         return BRW_REGISTER_TYPE_W;
+      case 32:
+         return BRW_REGISTER_TYPE_D;
+      case 64:
+         return BRW_REGISTER_TYPE_Q;
+      default:
+         unreachable("Invalid bit size");
+      }
+   case BRW_REGISTER_TYPE_UB:
+   case BRW_REGISTER_TYPE_UW:
+   case BRW_REGISTER_TYPE_UD:
+   case BRW_REGISTER_TYPE_UQ:
+      switch(bit_size) {
+      case 8:
+         return BRW_REGISTER_TYPE_UB;
+      case 16:
+         return BRW_REGISTER_TYPE_UW;
+      case 32:
+         return BRW_REGISTER_TYPE_UD;
+      case 64:
+         return BRW_REGISTER_TYPE_UQ;
+      default:
+         unreachable("Invalid bit size");
+      }
+   default:
+      unreachable("Unknown type");
+   }
+}
+
+
 #define INVALID_REG_TYPE    ((enum brw_reg_type)-1)
 #define INVALID_HW_REG_TYPE ((unsigned)-1)