Mesa (master): radv: synchronize Cmd{Set,Write}Event() using PS_DONE/CS_DONE events

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Module: Mesa
Branch: master
Commit: 9c65f1f11115248c672ddc2595434c3e9ac2ec3a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c65f1f11115248c672ddc2595434c3e9ac2ec3a

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Jan 22 14:46:30 2021 +0100

radv: synchronize Cmd{Set,Write}Event() using PS_DONE/CS_DONE events

This is probably rarely used but it can be easily implemented now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8650>

---

 src/amd/vulkan/radv_cmd_buffer.c | 35 ++++++++++++++++++++++++++++++-----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index f3ecc948be6..0b706336b5a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6612,6 +6612,22 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 		VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
 		VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
 
+	/* Flags that only require signaling post PS. */
+	VkPipelineStageFlags post_ps_flags =
+		post_index_fetch_flags |
+		VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
+		VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
+		VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
+		VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
+		VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT |
+		VK_PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR |
+		VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
+		VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
+
+	/* Flags that only require signaling post CS. */
+	VkPipelineStageFlags post_cs_flags =
+		VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT;
+
 	/* Make sure CP DMA is idle because the driver might have performed a
 	 * DMA operation for copying or filling buffers/images.
 	 */
@@ -6619,8 +6635,6 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 			 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
 		si_cp_dma_wait_for_idle(cmd_buffer);
 
-	/* TODO: Emit EOS events for syncing PS/CS stages. */
-
 	if (!(stageMask & ~top_of_pipe_flags)) {
 		/* Just need to sync the PFP engine. */
 		radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
@@ -6640,12 +6654,23 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 		radeon_emit(cs, va >> 32);
 		radeon_emit(cs, value);
 	} else {
-		/* Otherwise, sync all prior GPU work using an EOP event. */
+		unsigned event_type;
+
+		if (!(stageMask & ~post_ps_flags)) {
+			/* Sync previous fragment shaders. */
+			event_type = V_028A90_PS_DONE;
+		} else if (!(stageMask & ~post_cs_flags)) {
+			/* Sync previous compute shaders. */
+			event_type = V_028A90_CS_DONE;
+		} else {
+			/* Otherwise, sync all prior GPU work. */
+			event_type = V_028A90_BOTTOM_OF_PIPE_TS;
+		}
+
 		si_cs_emit_write_event_eop(cs,
 					   cmd_buffer->device->physical_device->rad_info.chip_class,
 					   radv_cmd_buffer_uses_mec(cmd_buffer),
-					   V_028A90_BOTTOM_OF_PIPE_TS, 0,
-					   EOP_DST_SEL_MEM,
+					   event_type, 0, EOP_DST_SEL_MEM,
 					   EOP_DATA_SEL_VALUE_32BIT, va, value,
 					   cmd_buffer->gfx9_eop_bug_va);
 	}