Mesa (staging/21.0): radv: Use stricter HW resolve swizzle compat check.

[GitLab Mirror]

Module: Mesa
Branch: staging/21.0
Commit: fd5c91e656ac5857ab9309dce6c8d310e5f45ba4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd5c91e656ac5857ab9309dce6c8d310e5f45ba4

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Jan 23 02:36:29 2021 +0100

radv: Use stricter HW resolve swizzle compat check.

D and linear are both DISPLAY micro tiling according to ac_surface
but don't work together. This fixes an issue with GFX9+.

This fixes the SkQP WritePixelsNonTexture_Gpu test.

Fixes: 69ea473eeb9 ("amd/addrlib: update to the latest version")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8665>
(cherry picked from commit 12ce72fcfcd07a1da4eb1b8bb2b3ebb1c2e651a7)

Conflicts:
	src/amd/vulkan/radv_meta_resolve.c

---

 .pick_status.json                  |  2 +-
 src/amd/vulkan/radv_meta_resolve.c | 20 ++++++++++++++++++--
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index e9495b2b6f3..e728f69194f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -373,7 +373,7 @@
         "description": "radv: Use stricter HW resolve swizzle compat check.",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "69ea473eeb91b2c4db26402c3bc2ed5799d26605"
     },
diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index 5a02dd5bb28..fc10f6e2f6d 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -353,6 +353,19 @@ enum radv_resolve_method {
 	RESOLVE_FRAGMENT,
 };
 
+static bool image_hw_resolve_compat(const struct radv_device *device,
+				    struct radv_image *src_image,
+				    struct radv_image *dst_image)
+{
+	if (device->physical_device->rad_info.chip_class >= GFX9) {
+		return dst_image->planes[0].surface.u.gfx9.surf.swizzle_mode ==
+		       src_image->planes[0].surface.u.gfx9.surf.swizzle_mode;
+	} else {
+		return dst_image->planes[0].surface.micro_tile_mode ==
+		       src_image->planes[0].surface.micro_tile_mode;
+	}
+}
+
 static void radv_pick_resolve_method_images(struct radv_device *device,
 					    struct radv_image *src_image,
 					    VkFormat src_format,
@@ -376,8 +389,11 @@ static void radv_pick_resolve_method_images(struct radv_device *device,
 		if (radv_layout_dcc_compressed(device, dest_image, dest_image_layout,
 		                               dest_render_loop, queue_mask)) {
 			*method = RESOLVE_FRAGMENT;
-		} else if (dest_image->planes[0].surface.micro_tile_mode !=
-		           src_image->planes[0].surface.micro_tile_mode) {
+		} else if (!image_hw_resolve_compat(device, src_image, dest_image)) {
+			/* The micro tile mode only needs to match for the HW
+			 * resolve path which is the default path for non-DCC
+			 * resolves.
+			 */
 			*method = RESOLVE_COMPUTE;
 		}