Mesa (master): radv: check if HTILE is enabled per-level instead of the entire image

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Module: Mesa
Branch: master
Commit: e7d898a26891a29518992fc137763d9fe77d1b0a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7d898a26891a29518992fc137763d9fe77d1b0a

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Dec 15 18:37:48 2020 +0100

radv: check if HTILE is enabled per-level instead of the entire image

With HTILE mipmaps support, we should check if the base level
currently in use supports compression.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8124>

---

 src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
 src/amd/vulkan/radv_meta_clear.c | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6e7cef3213a..2b3880c8d72 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2058,7 +2058,7 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 	};
 	struct radv_image *image = iview->image;
 
-	assert(radv_image_has_htile(image));
+	assert(radv_htile_enabled(image, range.baseMipLevel));
 
 	radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range,
 				   ds_clear_value, aspects);
@@ -6156,7 +6156,7 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
 {
 	struct radv_device *device = cmd_buffer->device;
 
-	if (!radv_image_has_htile(image))
+	if (!radv_htile_enabled(image, range->baseMipLevel))
 		return;
 
 	if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 65f459018a2..4f8434792d8 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -699,7 +699,8 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 	      clear_value.depth != 1.0) ||
 	     ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 		return false;
-	if (iview->base_mip == 0 &&
+	if (radv_htile_enabled(iview->image, iview->base_mip) &&
+	    iview->base_mip == 0 &&
 	    iview->base_layer == 0 &&
 	    iview->layer_count == iview->image->info.array_size &&
 	    radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop, queue_mask) &&