Mesa (master): intel: Produce a "constrained" output from gen_get_urb_config()
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Wed Jan 27 18:53:28 UTC 2021
Module: Mesa
Branch: master
Commit: a710145b5bf60ef47460eea87b072077e3ddaa72
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a710145b5bf60ef47460eea87b072077e3ddaa72
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jan 25 21:41:48 2021 -0800
intel: Produce a "constrained" output from gen_get_urb_config()
When calculating a URB configuration, we start with a notion of how
much space each stage /wants/ (to achieve the maximum amount of
concurrency), but sometimes fall back to giving it less than that,
because we don't have enough space. (Typically, this happens when
the per-stage size is large, or there are many stages, or both.)
We now output a "constrained" boolean which is true if we weren't
able to satisfy all the "wants" due to a lack of space.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8721>
---
src/gallium/drivers/iris/iris_state.c | 4 +++-
src/intel/blorp/blorp_genX_exec.h | 3 ++-
src/intel/common/gen_l3_config.h | 3 ++-
src/intel/common/gen_urb_config.c | 7 ++++++-
src/intel/vulkan/genX_pipeline.c | 4 +++-
src/mesa/drivers/dri/i965/gen7_urb.c | 3 ++-
6 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index f240cdac0bf..151182b62d2 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5594,13 +5594,15 @@ iris_upload_dirty_render_state(struct iris_context *ice,
assert(size[i] != 0);
}
+ bool constrained;
unsigned entries[4], start[4];
gen_get_urb_config(&batch->screen->devinfo,
batch->screen->l3_config_3d,
ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
size, entries, start,
- &ice->state.urb_deref_block_size);
+ &ice->state.urb_deref_block_size,
+ &constrained);
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 5eb4419d7f2..f0872eb0be8 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -217,10 +217,11 @@ emit_urb_config(struct blorp_batch *batch,
const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
unsigned entries[4], start[4];
+ bool constrained;
gen_get_urb_config(batch->blorp->compiler->devinfo,
blorp_get_l3_config(batch),
false, false, entry_size,
- entries, start, deref_block_size);
+ entries, start, deref_block_size, &constrained);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
diff --git a/src/intel/common/gen_l3_config.h b/src/intel/common/gen_l3_config.h
index 443a8949bfe..352ba569c46 100644
--- a/src/intel/common/gen_l3_config.h
+++ b/src/intel/common/gen_l3_config.h
@@ -103,6 +103,7 @@ void gen_get_urb_config(const struct gen_device_info *devinfo,
bool tess_present, bool gs_present,
const unsigned entry_size[4],
unsigned entries[4], unsigned start[4],
- enum gen_urb_deref_block_size *deref_block_size);
+ enum gen_urb_deref_block_size *deref_block_size,
+ bool *constrained);
#endif /* GEN_L3_CONFIG_H */
diff --git a/src/intel/common/gen_urb_config.c b/src/intel/common/gen_urb_config.c
index 0b819f4c937..c84b5afb2d7 100644
--- a/src/intel/common/gen_urb_config.c
+++ b/src/intel/common/gen_urb_config.c
@@ -56,6 +56,8 @@
* \param[in] entry_size - the URB entry size (from the shader compiler)
* \param[out] entries - the number of URB entries for each stage
* \param[out] start - the starting offset for each stage
+ * \param[out] deref_block_size - deref block size for 3DSTATE_SF
+ * \param[out] constrained - true if we wanted more space than we had
*/
void
gen_get_urb_config(const struct gen_device_info *devinfo,
@@ -63,7 +65,8 @@ gen_get_urb_config(const struct gen_device_info *devinfo,
bool tess_present, bool gs_present,
const unsigned entry_size[4],
unsigned entries[4], unsigned start[4],
- enum gen_urb_deref_block_size *deref_block_size)
+ enum gen_urb_deref_block_size *deref_block_size,
+ bool *constrained)
{
unsigned urb_size_kB = gen_get_l3_config_urb_size(devinfo, l3_cfg);
@@ -174,6 +177,8 @@ gen_get_urb_config(const struct gen_device_info *devinfo,
assert(total_needs <= urb_chunks);
+ *constrained = total_needs + total_wants > urb_chunks;
+
/* Mete out remaining space (if any) in proportion to "wants". */
unsigned remaining_space = MIN2(urb_chunks - total_needs, total_wants);
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index bd119e92a44..6fb16b0536e 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -272,11 +272,13 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
unsigned entries[4];
unsigned start[4];
+ bool constrained;
gen_get_urb_config(devinfo, l3_config,
active_stages &
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
active_stages & VK_SHADER_STAGE_GEOMETRY_BIT,
- entry_size, entries, start, deref_block_size);
+ entry_size, entries, start, deref_block_size,
+ &constrained);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index abc922a86a3..6898728dbc5 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -247,9 +247,10 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
unsigned entries[4];
unsigned start[4];
+ bool constrained;
gen_get_urb_config(devinfo, brw->l3.config,
tess_present, gs_present, entry_size,
- entries, start, NULL);
+ entries, start, NULL, &constrained);
if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
gen7_emit_vs_workaround_flush(brw);
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