Mesa (staging/21.0): aco: fix nir_intrinsic_ballot with wave32

[GitLab Mirror]

Module: Mesa
Branch: staging/21.0
Commit: 1c4a92a7cdbeaee9b10703364c8ae338e92ffc03
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c4a92a7cdbeaee9b10703364c8ae338e92ffc03

Author: Daniel Schürmann <daniel at schuermann.dev>
Date:   Mon Jan 25 18:37:29 2021 +0100

aco: fix nir_intrinsic_ballot with wave32

Found by inspection.

Fixes: 21db083504fde3100f0b528f683a087357f5aaff ('aco/wave32: Allow setting the subgroup ballot size to 64-bit.')

Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8703>
(cherry picked from commit b06609e90324e8c445eb71eec39158a893c574c3)

---

 .pick_status.json                              | 2 +-
 src/amd/compiler/aco_instruction_selection.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index b506d865fba..0caa7855427 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -391,7 +391,7 @@
         "description": "aco: fix nir_intrinsic_ballot with wave32",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "21db083504fde3100f0b528f683a087357f5aaff"
     },
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 4e3fc57f977..92b3d4aa3fc 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8139,7 +8139,7 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
       Definition tmp = bld.def(dst.regClass());
-      Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
+      Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(bld.lm);
       if (instr->src[0].ssa->bit_size == 1) {
          assert(src.regClass() == bld.lm);
          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);