Mesa (master): radv: re-disable TC-compat HTILE for D32S8 on all generations

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Module: Mesa
Branch: master
Commit: c092ff2f2f57a4cc559507420f7f49eaf9b1d8ab
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c092ff2f2f57a4cc559507420f7f49eaf9b1d8ab

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Jan 29 12:14:18 2021 +0100

radv: re-disable TC-compat HTILE for D32S8 on all generations

This actually introduced some VRS related regressions and some others.

Fixes: cc5b6a0e897 ("radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8777>

---

 src/amd/vulkan/radv_image.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 0229db314c0..94a55b46ed9 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -95,13 +95,13 @@ radv_use_tc_compat_htile_for_image(struct radv_device *device,
 				    VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
 		return false;
 
-	if (device->physical_device->rad_info.chip_class < GFX9) {
-		/* FIXME: for some reason TC compat with 2/4/8 samples breaks
-		 * some cts tests - disable for now.
-		 */
-		if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
-			return false;
+	/* FIXME: for some reason TC compat with 2/4/8 samples breaks
+	 * some cts tests - disable for now.
+	 */
+	if (pCreateInfo->samples >= 2 && format == VK_FORMAT_D32_SFLOAT_S8_UINT)
+		return false;
 
+	if (device->physical_device->rad_info.chip_class < GFX9) {
 		/* GFX9+ supports compression for both 32-bit and 16-bit depth
 		 * surfaces, while GFX8 only supports 32-bit natively. Though,
 		 * the driver allows TC-compat HTILE for 16-bit depth surfaces