Mesa (main): radv: implement VK_EXT_color_write_enable
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Fri Jul 2 10:18:28 UTC 2021
Module: Mesa
Branch: main
Commit: 9a95aba3777bcb42de28ddc117810ee73eae4153
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a95aba3777bcb42de28ddc117810ee73eae4153
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Mar 18 15:25:42 2021 +0100
radv: implement VK_EXT_color_write_enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11530>
---
src/amd/vulkan/radv_cmd_buffer.c | 53 +++++++++++++++++++++++++++++++++++++---
src/amd/vulkan/radv_device.c | 1 +
src/amd/vulkan/radv_meta.c | 7 +++++-
src/amd/vulkan/radv_meta.h | 2 ++
src/amd/vulkan/radv_pipeline.c | 18 +++++++++++++-
src/amd/vulkan/radv_private.h | 18 ++++++++------
6 files changed, 87 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 37ee54d8103..276dd685154 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -116,6 +116,7 @@ const struct radv_dynamic_state default_dynamic_state = {
.primitive_restart_enable = 0u,
.rasterizer_discard_enable = 0u,
.logic_op = 0u,
+ .color_write_enable = 0xffffffffu,
};
static void
@@ -335,6 +336,13 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy
}
}
+ if (copy_mask & RADV_DYNAMIC_COLOR_WRITE_ENABLE) {
+ if (dest->color_write_enable != src->color_write_enable) {
+ dest->color_write_enable = src->color_write_enable;
+ dest_mask |= RADV_DYNAMIC_COLOR_WRITE_ENABLE;
+ }
+ }
+
cmd_buffer->state.dirty |= dest_mask;
}
@@ -1246,9 +1254,7 @@ radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&
(settings.context_states_per_bin > 1 || settings.persistent_states_per_bin > 1);
bool break_for_new_cb_target_mask =
- (!cmd_buffer->state.emitted_pipeline ||
- cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
- cmd_buffer->state.pipeline->graphics.cb_target_mask) &&
+ (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) &&
settings.context_states_per_bin > 1;
if (!break_for_new_ps && !break_for_new_cb_target_mask)
@@ -1312,6 +1318,12 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (!cmd_buffer->state.emitted_pipeline)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
+ if (!cmd_buffer->state.emitted_pipeline ||
+ cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
+ pipeline->graphics.cb_target_mask) {
+ cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;
+ }
+
radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
if (!cmd_buffer->state.emitted_pipeline ||
@@ -1623,6 +1635,16 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer)
radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, cb_color_control);
}
+static void
+radv_emit_color_write_enable(struct radv_cmd_buffer *cmd_buffer)
+{
+ struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
+ struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK,
+ pipeline->graphics.cb_target_mask & d->color_write_enable);
+}
+
static void
radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
struct radv_color_buffer_info *cb, struct radv_image_view *iview,
@@ -2626,6 +2648,9 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
if (states & RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP)
radv_emit_logic_op(cmd_buffer);
+ if (states & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE)
+ radv_emit_color_write_enable(cmd_buffer);
+
cmd_buffer->state.dirty &= ~states;
}
@@ -4803,6 +4828,28 @@ radv_CmdSetLogicOpEXT(VkCommandBuffer commandBuffer, VkLogicOp logicOp)
state->dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
}
+void
+radv_CmdSetColorWriteEnableEXT(VkCommandBuffer commandBuffer, uint32_t attachmentCount,
+ const VkBool32 *pColorWriteEnables)
+{
+ RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
+ struct radv_cmd_state *state = &cmd_buffer->state;
+ uint32_t color_write_enable = 0;
+
+ assert(attachmentCount < MAX_RTS);
+
+ for (uint32_t i = 0; i < attachmentCount; i++) {
+ color_write_enable |= pColorWriteEnables[i] ? (0xfu << (i * 4)) : 0;
+ }
+
+ if (state->dynamic.color_write_enable == color_write_enable)
+ return;
+
+ state->dynamic.color_write_enable = color_write_enable;
+
+ state->dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;
+}
+
void
radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount,
const VkCommandBuffer *pCmdBuffers)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 16bbb10f125..eb97e3dfe30 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -451,6 +451,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
.EXT_4444_formats = true,
.EXT_buffer_device_address = true,
.EXT_calibrated_timestamps = RADV_SUPPORT_CALIBRATED_TIMESTAMPS,
+ .EXT_color_write_enable = false,
.EXT_conditional_rendering = true,
.EXT_conservative_rasterization = device->rad_info.chip_class >= GFX9,
.EXT_custom_border_color = true,
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index bc3729e32e7..fe676d46614 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -99,6 +99,8 @@ radv_meta_save(struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_
state->rasterizer_discard_enable = cmd_buffer->state.dynamic.rasterizer_discard_enable;
state->logic_op = cmd_buffer->state.dynamic.logic_op;
+
+ state->color_write_enable = cmd_buffer->state.dynamic.color_write_enable;
}
if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
@@ -190,6 +192,8 @@ radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buf
cmd_buffer->state.dynamic.logic_op = state->logic_op;
+ cmd_buffer->state.dynamic.color_write_enable = state->color_write_enable;
+
cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | RADV_CMD_DIRTY_DYNAMIC_SCISSOR |
RADV_CMD_DIRTY_DYNAMIC_CULL_MODE | RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
@@ -199,7 +203,8 @@ radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buf
RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP |
RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE | RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE |
- RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
+ RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE | RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP |
+ RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;
}
if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index da9c00441e1..54ce4fb1608 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -96,6 +96,8 @@ struct radv_meta_saved_state {
bool rasterizer_discard_enable;
unsigned logic_op;
+
+ uint32_t color_write_enable;
};
VkResult radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4263a593531..fb1d95e63cf 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1323,6 +1323,8 @@ radv_dynamic_state_mask(VkDynamicState state)
return RADV_DYNAMIC_LOGIC_OP;
case VK_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE_EXT:
return RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
+ case VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT:
+ return RADV_DYNAMIC_COLOR_WRITE_ENABLE;
default:
unreachable("Unhandled dynamic state");
}
@@ -1399,6 +1401,9 @@ radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateIn
!radv_pipeline_is_blend_enabled(pCreateInfo))
states &= ~RADV_DYNAMIC_BLEND_CONSTANTS;
+ if (!subpass->has_color_att)
+ states &= ~RADV_DYNAMIC_COLOR_WRITE_ENABLE;
+
return states;
}
@@ -1729,6 +1734,18 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
}
}
+ if (states & RADV_DYNAMIC_COLOR_WRITE_ENABLE) {
+ const VkPipelineColorWriteCreateInfoEXT *color_write_info = vk_find_struct_const(
+ pCreateInfo->pColorBlendState->pNext, PIPELINE_COLOR_WRITE_CREATE_INFO_EXT);
+ if (color_write_info) {
+ dynamic->color_write_enable = 0;
+ for (uint32_t i = 0; i < color_write_info->attachmentCount; i++) {
+ dynamic->color_write_enable |=
+ color_write_info->pColorWriteEnables[i] ? (0xfu << (i * 4)) : 0;
+ }
+ }
+ }
+
pipeline->dynamic_state.mask = states;
}
@@ -4232,7 +4249,6 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
- radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d98f8805f68..39ab7b50322 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1014,7 +1014,8 @@ enum radv_dynamic_state_bits {
RADV_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
RADV_DYNAMIC_LOGIC_OP = 1ull << 26,
RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
- RADV_DYNAMIC_ALL = (1ull << 28) - 1,
+ RADV_DYNAMIC_COLOR_WRITE_ENABLE = 1ull << 28,
+ RADV_DYNAMIC_ALL = (1ull << 29) - 1,
};
enum radv_cmd_dirty_bits {
@@ -1048,12 +1049,13 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP = 1ull << 26,
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
- RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 28) - 1,
- RADV_CMD_DIRTY_PIPELINE = 1ull << 28,
- RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 29,
- RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 30,
- RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 31,
- RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 32,
+ RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE = 1ull << 28,
+ RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 29) - 1,
+ RADV_CMD_DIRTY_PIPELINE = 1ull << 29,
+ RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 30,
+ RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 31,
+ RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 32,
+ RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 33
};
enum radv_cmd_flush_bits {
@@ -1231,6 +1233,8 @@ struct radv_dynamic_state {
bool rasterizer_discard_enable;
unsigned logic_op;
+
+ uint32_t color_write_enable;
};
extern const struct radv_dynamic_state default_dynamic_state;
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