Mesa (main): radv: allow more fast clears for depth surfaces without TC-compat HTILE

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Module: Mesa
Branch: main
Commit: e58ab64223111ea0ce10cc86c762cffa18b108c5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e58ab64223111ea0ce10cc86c762cffa18b108c5

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Apr  5 14:19:42 2021 +0200

radv: allow more fast clears for depth surfaces without TC-compat HTILE

With HTILE only, all values between 0.0 and 1.0 are fetchable.
This should allow more fast clears for depth surfaces where
TC-compat HTILE is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>

---

 src/amd/vulkan/radv_meta_clear.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index ca99fc0b14a..3ad4040fe1c 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -980,9 +980,10 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_
        (clear_value.depth < 0.0 || clear_value.depth > 1.0))
       return false;
 
-   if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && !radv_is_fast_clear_depth_allowed(clear_value)) ||
-       ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
-        !radv_is_fast_clear_stencil_allowed(clear_value)))
+   if (radv_image_is_tc_compat_htile(iview->image) &&
+       (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && !radv_is_fast_clear_depth_allowed(clear_value)) ||
+        ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
+         !radv_is_fast_clear_stencil_allowed(clear_value))))
       return false;
 
    return true;