Mesa (main): iris: Delete unused bo->cache_coherent flag

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Module: Mesa
Branch: main
Commit: 6e55890b6c7e3fbab241778ed702f7d68c2d3adf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e55890b6c7e3fbab241778ed702f7d68c2d3adf

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Jun 28 11:42:24 2021 -0700

iris: Delete unused bo->cache_coherent flag

This was used in the heuristics for deciding whether to CPU map,
but those have since been deleted, so this is now unused.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>

---

 src/gallium/drivers/iris/iris_bufmgr.c | 8 ++------
 src/gallium/drivers/iris/iris_bufmgr.h | 5 -----
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c
index 554e7a81d6b..2c8543103b0 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -651,7 +651,6 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
    bo->name = name;
    p_atomic_set(&bo->refcount, 1);
    bo->reusable = bucket && bufmgr->bo_reuse;
-   bo->cache_coherent = bufmgr->has_llc;
    bo->index = -1;
    bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
 
@@ -667,8 +666,8 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
    /* On integrated GPUs, enable snooping to ensure coherency if needed.
     * For discrete, we instead use SMEM and avoid WB maps for coherency.
     */
-   if (bufmgr->vram.size == 0 &&
-       (flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
+   if ((flags & BO_ALLOC_COHERENT) &&
+       !bufmgr->has_llc && bufmgr->vram.size == 0) {
       struct drm_i915_gem_caching arg = {
          .handle = bo->gem_handle,
          .caching = 1,
@@ -676,7 +675,6 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
       if (intel_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg) != 0)
          goto err_free;
 
-      bo->cache_coherent = true;
       bo->reusable = false;
    }
 
@@ -735,7 +733,6 @@ iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
 
    p_atomic_set(&bo->refcount, 1);
    bo->userptr = true;
-   bo->cache_coherent = true;
    bo->index = -1;
    bo->idle = true;
    bo->mmap_mode = IRIS_MMAP_WB;
@@ -1338,7 +1335,6 @@ iris_bo_mark_exported_locked(struct iris_bo *bo)
        * display HW. So make sure our CPU mappings don't assume cache
        * coherency since display is outside that cache.
        */
-      bo->cache_coherent = false;
       bo->exported = true;
       bo->reusable = false;
    }
diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index 7b235de5161..ec9f39da9d9 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -229,11 +229,6 @@ struct iris_bo {
    /** Has this buffer been exported to external clients? */
    bool exported;
 
-   /**
-    * Boolean of whether this buffer is cache coherent
-    */
-   bool cache_coherent;
-
    /**
     * Boolean of whether this buffer points into user memory
     */