Mesa (main): asahi: Set bit for psiz

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Module: Mesa
Branch: main
Commit: 2468b123bb029e35f29a0a375ed86d0e2ada695d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2468b123bb029e35f29a0a375ed86d0e2ada695d

Author: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Date:   Sun Jul 11 16:42:33 2021 -0400

asahi: Set bit for psiz

Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11818>

---

 src/asahi/compiler/agx_compile.c      | 5 +++++
 src/asahi/compiler/agx_compile.h      | 3 +++
 src/gallium/drivers/asahi/agx_state.c | 4 +++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index e6aa627a846..76d133cbb10 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -1285,6 +1285,11 @@ agx_compile_shader_nir(nir_shader *nir,
    ctx->stage = nir->info.stage;
    list_inithead(&ctx->blocks);
 
+   if (ctx->stage == MESA_SHADER_VERTEX) {
+      out->writes_psiz = nir->info.outputs_written &
+         BITFIELD_BIT(VARYING_SLOT_PSIZ);
+   }
+
    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 
    /* Lower large arrays to scratch and small arrays to csel */
diff --git a/src/asahi/compiler/agx_compile.h b/src/asahi/compiler/agx_compile.h
index c927377b971..894155c99f4 100644
--- a/src/asahi/compiler/agx_compile.h
+++ b/src/asahi/compiler/agx_compile.h
@@ -91,6 +91,9 @@ struct agx_shader_info {
 
    /* Does the shader read the tilebuffer? */
    bool reads_tib;
+
+   /* Does the shader write point size? */
+   bool writes_psiz;
 };
 
 #define AGX_MAX_RTS (8)
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index dc477256ccd..0ee33226781 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -1314,7 +1314,9 @@ demo_linkage(struct agx_compiled_shader *vs, struct agx_pool *pool)
 
    agx_pack(t.cpu, LINKAGE, cfg) {
       cfg.varying_count = vs->info.varyings.nr_slots;
-      cfg.unk_1 = 0x210000; // varyings otherwise wrong
+
+      // 0x2 for fragcoordz, 0x1 for varyings at all
+      cfg.unk_1 = 0x210000 | (vs->info.writes_psiz ? 0x40000 : 0);
    };
 
    return t.gpu;