Mesa (main): intel/compiler: Track latency/perf of LSC fences

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Module: Mesa
Branch: main
Commit: 91dcbf1f56ce5452426e5f2644dce0024812c9ba
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=91dcbf1f56ce5452426e5f2644dce0024812c9ba

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Tue May 25 11:31:10 2021 +0300

intel/compiler: Track latency/perf of LSC fences

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11759>

---

 src/intel/compiler/brw_ir_performance.cpp        | 1 +
 src/intel/compiler/brw_schedule_instructions.cpp | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index d4a0a875c6b..edec07a909a 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -1106,6 +1106,7 @@ namespace {
                                      10 /* XXX */, 100 /* XXX */, 0, 0,
                                      0, 0);
 
+            case LSC_OP_FENCE:
             case LSC_OP_ATOMIC_INC:
             case LSC_OP_ATOMIC_DEC:
             case LSC_OP_ATOMIC_LOAD:
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index 797c2097bb6..e19a9e5416d 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -538,6 +538,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
          case LSC_OP_STORE_CMASK:
             latency = 300;
             break;
+         case LSC_OP_FENCE:
          case LSC_OP_ATOMIC_INC:
          case LSC_OP_ATOMIC_DEC:
          case LSC_OP_ATOMIC_LOAD: