Mesa (main): intel/compiler: document register types

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Module: Mesa
Branch: main
Commit: f3742b9c131744e3b3c5f7dc35de408f6f61bbae
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3742b9c131744e3b3c5f7dc35de408f6f61bbae

Author: Marcin Ślusarz <marcin.slusarz at intel.com>
Date:   Thu Jul  1 14:46:48 2021 +0200

intel/compiler: document register types

Signed-off-by: Marcin Ślusarz <marcin.slusarz at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11677>

---

 src/intel/compiler/brw_reg.h      |  3 ++-
 src/intel/compiler/brw_reg_type.h | 30 +++++++++++++++---------------
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 069d80f1a9a..4130e0a8b88 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -327,9 +327,10 @@ type_sz(unsigned type)
       return 4;
    case BRW_REGISTER_TYPE_UW:
    case BRW_REGISTER_TYPE_W:
+   case BRW_REGISTER_TYPE_HF:
+   /* [U]V components are 4-bit, but HW unpacks them to 16-bit (2 bytes) */
    case BRW_REGISTER_TYPE_UV:
    case BRW_REGISTER_TYPE_V:
-   case BRW_REGISTER_TYPE_HF:
       return 2;
    case BRW_REGISTER_TYPE_UB:
    case BRW_REGISTER_TYPE_B:
diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h
index 0013c9bb6aa..aaa753acb36 100644
--- a/src/intel/compiler/brw_reg_type.h
+++ b/src/intel/compiler/brw_reg_type.h
@@ -45,24 +45,24 @@ struct intel_device_info;
  */
 enum PACKED brw_reg_type {
    /** Floating-point types: @{ */
-   BRW_REGISTER_TYPE_NF,
-   BRW_REGISTER_TYPE_DF,
-   BRW_REGISTER_TYPE_F,
-   BRW_REGISTER_TYPE_HF,
-   BRW_REGISTER_TYPE_VF,
+   BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */
+   BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */
+   BRW_REGISTER_TYPE_F,  /* 32-bit float */
+   BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */
+   BRW_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */
    /** @} */
 
    /** Integer types: @{ */
-   BRW_REGISTER_TYPE_Q,
-   BRW_REGISTER_TYPE_UQ,
-   BRW_REGISTER_TYPE_D,
-   BRW_REGISTER_TYPE_UD,
-   BRW_REGISTER_TYPE_W,
-   BRW_REGISTER_TYPE_UW,
-   BRW_REGISTER_TYPE_B,
-   BRW_REGISTER_TYPE_UB,
-   BRW_REGISTER_TYPE_V,
-   BRW_REGISTER_TYPE_UV,
+   BRW_REGISTER_TYPE_Q,  /* 64-bit   signed integer (quad word) */
+   BRW_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */
+   BRW_REGISTER_TYPE_D,  /* 32-bit   signed integer (double word) */
+   BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */
+   BRW_REGISTER_TYPE_W,  /* 16-bit   signed integer (word) */
+   BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */
+   BRW_REGISTER_TYPE_B,  /*  8-bit   signed integer (byte) */
+   BRW_REGISTER_TYPE_UB, /*  8-bit unsigned integer (byte) */
+   BRW_REGISTER_TYPE_V,  /* vector of 8   signed 4-bit integers (treated as W) */
+   BRW_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */
    /** @} */
 
    BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV