Mesa (main): freedreno/ir3: Get reg_size_vec4 from fd_dev_info

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Module: Mesa
Branch: main
Commit: f4cfb5a61ecf4deee75205f87d1df875ed1de144
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4cfb5a61ecf4deee75205f87d1df875ed1de144

Author: Rob Clark <robdclark at chromium.org>
Date:   Thu Jul  8 10:02:19 2021 -0700

freedreno/ir3: Get reg_size_vec4 from fd_dev_info

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>

---

 src/freedreno/common/freedreno_dev_info.h |  2 ++
 src/freedreno/common/freedreno_devices.py |  3 +++
 src/freedreno/ir3/ir3_compiler.c          | 10 +++-------
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index 77756a290bd..bed3c2c60d1 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -57,6 +57,8 @@ struct fd_dev_info {
          /* Information for private memory calculations */
          uint32_t fibers_per_sp;
 
+         uint32_t reg_size_vec4;
+
          /* Whether the PC_MULTIVIEW_MASK register exists. */
          bool supports_multiview_mask;
 
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 8404d4fc6d6..4de74d65ec0 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -174,12 +174,14 @@ add_gpus([
 # a615, a618, a630:
 a6xx_gen1 = dict(
         fibers_per_sp = 128 * 16,
+        reg_size_vec4 = 96,
         ccu_cntl_gmem_unk2 = True,
     )
 
 # a640, a680:
 a6xx_gen2 = dict(
         fibers_per_sp = 128 * 4 * 16,
+        reg_size_vec4 = 96,
         supports_multiview_mask = True,
         has_z24uint_s8uint = True,
     )
@@ -187,6 +189,7 @@ a6xx_gen2 = dict(
 # a650:
 a6xx_gen3 = dict(
         fibers_per_sp = 128 * 2 * 16,
+        reg_size_vec4 = 64,
         supports_multiview_mask = True,
         has_z24uint_s8uint = True,
         tess_use_shared = True,
diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index 54fe98bcaa7..e3a9b3584f0 100644
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -136,13 +136,9 @@ ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
       compiler->max_const_safe = 256;
    }
 
-   if (compiler->gpu_id == 650) {
-      /* This changed mid-generation for a650, so that using r32.x and above
-       * requires using the smallest threadsize.
-       */
-      compiler->reg_size_vec4 = 64;
-   } else if (compiler->gpu_id >= 600) {
-      compiler->reg_size_vec4 = 96;
+   if (compiler->gpu_id >= 600) {
+      compiler->reg_size_vec4 =
+            fd_dev_info(compiler->gpu_id)->a6xx.reg_size_vec4;
    } else if (compiler->gpu_id >= 400) {
       /* On a4xx-a5xx, using r24.x and above requires using the smallest
        * threadsize.