Mesa (main): intel/compiler: Handle ternary add in lower_simd_width

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Module: Mesa
Branch: main
Commit: ef29bb6bc53bf07097ddaf6329c8892f50168e7e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef29bb6bc53bf07097ddaf6329c8892f50168e7e

Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date:   Wed Jul 21 15:24:29 2021 -0700

intel/compiler: Handle ternary add in lower_simd_width

We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.

Reported-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>

---

 src/intel/compiler/brw_fs.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6052d3760ef..8499a35b2c5 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7322,6 +7322,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
    case BRW_OPCODE_SAD2:
    case BRW_OPCODE_MAD:
    case BRW_OPCODE_LRP:
+   case BRW_OPCODE_ADD3:
    case FS_OPCODE_PACK:
    case SHADER_OPCODE_SEL_EXEC:
    case SHADER_OPCODE_CLUSTER_BROADCAST: