Mesa (main): v3d/simulator: wait for cache flushes

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Module: Mesa
Branch: main
Commit: 7f3e34bcb4d9188aa06a0bafd7fd62f13ca92bed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f3e34bcb4d9188aa06a0bafd7fd62f13ca92bed

Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date:   Tue May 25 23:52:48 2021 +0200

v3d/simulator: wait for cache flushes

Current code just assumes that flushes are instant, as simulator
doesn't really model the caches. So right now we have just an assert
that the flush has been done.

But that can change on the future, so let's change the assert for a
wait.

Note that for the l1t case we are writing on the field TMUWCF. So I
understand that then we need to wait for TMUWCF_SET, even if the
previous code was using L2TFLS_SET.

This also happpens on the kernel side. We need to check if this was a
typo on the kernel side.

v2 (from Juan feedback)
   * Add comment about the TMUWCF vs L2TFLS difference between this
     commit and the kernel.

Reviewed-by: Juan A. Suarez <jasuarez at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11039>

---

 src/broadcom/simulator/v3dx_simulator.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/broadcom/simulator/v3dx_simulator.c b/src/broadcom/simulator/v3dx_simulator.c
index 9fdf5921566..6052f100d38 100644
--- a/src/broadcom/simulator/v3dx_simulator.c
+++ b/src/broadcom/simulator/v3dx_simulator.c
@@ -98,6 +98,22 @@ v3d_invalidate_l2t(struct v3d_hw *v3d)
                   (V3D_CACHE_FLUSH_MODE_FLUSH << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
 }
 
+/*
+ * Wait for l2tcactl, used for flushes.
+ *
+ * FIXME: for a multicore scenario we should pass here the core. All wrapper
+ * assumes just one core, so would be better to handle that on that case.
+ */
+static UNUSED void v3d_core_wait_l2tcactl(struct v3d_hw *v3d,
+                                          uint32_t ctrl)
+{
+   assert(!(ctrl & ~(V3D_CTL_0_L2TCACTL_TMUWCF_SET | V3D_CTL_0_L2TCACTL_L2TFLS_SET)));
+
+   while (V3D_READ(V3D_CTL_0_L2TCACTL) & ctrl) {
+           v3d_hw_tick(v3d);
+   }
+}
+
 /* Flushes dirty texture cachelines from the L1 write combiner */
 static void
 v3d_flush_l1td(struct v3d_hw *v3d)
@@ -105,7 +121,13 @@ v3d_flush_l1td(struct v3d_hw *v3d)
         V3D_WRITE(V3D_CTL_0_L2TCACTL,
                   V3D_CTL_0_L2TCACTL_TMUWCF_SET);
 
-        assert(!(V3D_READ(V3D_CTL_0_L2TCACTL) & V3D_CTL_0_L2TCACTL_L2TFLS_SET));
+        /* Note: here the kernel (and previous versions of the simulator
+         * wrapper) is using V3D_CTL_0_L2TCACTL_L2TFLS_SET, as with l2t. We
+         * understand that it makes more sense to do like this. We need to
+         * confirm which one is doing it correctly. So far things work fine on
+         * the simulator this way.
+         */
+        v3d_core_wait_l2tcactl(v3d, V3D_CTL_0_L2TCACTL_TMUWCF_SET);
 }
 
 /* Flushes dirty texture L2 cachelines */
@@ -118,7 +140,7 @@ v3d_flush_l2t(struct v3d_hw *v3d)
                   V3D_CTL_0_L2TCACTL_L2TFLS_SET |
                   (V3D_CACHE_FLUSH_MODE_CLEAN << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
 
-        assert(!(V3D_READ(V3D_CTL_0_L2TCACTL) & V3D_CTL_0_L2TCACTL_L2TFLS_SET));
+        v3d_core_wait_l2tcactl(v3d, V3D_CTL_0_L2TCACTL_L2TFLS_SET);
 }
 
 /* Invalidates the slice caches.  These are read-only caches. */