Mesa (main): intel/nir,i965: Move HW generation check for UBO pushing to i965
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Thu Jun 3 05:52:36 UTC 2021
Module: Mesa
Branch: main
Commit: f63410eee68889f3c838906f99c28bdea42e9af2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f63410eee68889f3c838906f99c28bdea42e9af2
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Jun 2 14:01:24 2021 -0500
intel/nir,i965: Move HW generation check for UBO pushing to i965
Iris only runs on BDW+ and ANV already handles this by not even trying
on anything older than HSW. The only driver benefiting from this common
check is i965. Moving it out makes the pass more generic and if some
driver comes along which can push UBOs on IVB, it should work for that.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11145>
---
src/intel/compiler/brw_nir_analyze_ubo_ranges.c | 7 -------
src/mesa/drivers/dri/i965/brw_context.c | 6 ++++++
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_gs.c | 6 ++++--
src/mesa/drivers/dri/i965/brw_tcs.c | 6 ++++--
src/mesa/drivers/dri/i965/brw_tes.c | 6 ++++--
src/mesa/drivers/dri/i965/brw_vs.c | 6 ++++--
src/mesa/drivers/dri/i965/brw_wm.c | 6 ++++--
8 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
index 2fa4dd5908a..3ab618ee123 100644
--- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
+++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
@@ -200,13 +200,6 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
const struct brw_vs_prog_key *vs_key,
struct brw_ubo_range out_ranges[4])
{
- const struct intel_device_info *devinfo = compiler->devinfo;
-
- if (devinfo->verx10 <= 70) {
- memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
- return;
- }
-
void *mem_ctx = ralloc_context(NULL);
struct ubo_analysis_state state = {
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index c2ab5c06cfa..464a54338eb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1039,6 +1039,12 @@ brw_create_context(gl_api api,
brw->has_swizzling = screen->hw_has_swizzling;
+ /* We don't push UBOs on IVB and earlier because the restrictions on
+ * 3DSTATE_CONSTANT_* make it really annoying to use push constants
+ * without dynamic state base address.
+ */
+ brw->can_push_ubos = devinfo->verx10 >= 75;
+
brw->isl_dev = screen->isl_dev;
brw->vs.base.stage = MESA_SHADER_VERTEX;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 506cbddd62f..17791286328 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -826,6 +826,8 @@ struct brw_context
bool has_separate_stencil;
bool has_swizzling;
+ bool can_push_ubos;
+
/** Derived stencil states. */
bool stencil_enabled;
bool stencil_two_sided;
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 9c1d31ed0ec..ea6aa3ee94c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -104,8 +104,10 @@ brw_codegen_gs_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &gp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
- brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
- prog_data.base.base.ubo_ranges);
+ if (brw->can_push_ubos) {
+ brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
+ prog_data.base.base.ubo_ranges);
+ }
uint64_t outputs_written = nir->info.outputs_written;
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 786f1cb2ec7..faf6ad57b0c 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -65,8 +65,10 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tcp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
- brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
- prog_data.base.base.ubo_ranges);
+ if (brw->can_push_ubos) {
+ brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
+ prog_data.base.base.ubo_ranges);
+ }
} else {
/* Upload the Patch URB Header as the first two uniforms.
* Do the annoying scrambling so the shader doesn't have to.
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 4330ecebeb2..9cafd2dd848 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -57,8 +57,10 @@ brw_codegen_tes_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tep->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
- brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
- prog_data.base.base.ubo_ranges);
+ if (brw->can_push_ubos) {
+ brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
+ prog_data.base.base.ubo_ranges);
+ }
int st_index = -1;
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 47c21787999..da37cfe11ac 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -142,8 +142,10 @@ brw_codegen_vs_prog(struct brw_context *brw,
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &vp->program,
&prog_data.base.base,
compiler->scalar_stage[MESA_SHADER_VERTEX]);
- brw_nir_analyze_ubo_ranges(compiler, nir, key,
- prog_data.base.base.ubo_ranges);
+ if (brw->can_push_ubos) {
+ brw_nir_analyze_ubo_ranges(compiler, nir, key,
+ prog_data.base.base.ubo_ranges);
+ }
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &vp->program,
&prog_data.base.base);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 18cd183d9a7..615ab10aa45 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -94,8 +94,10 @@ brw_codegen_wm_prog(struct brw_context *brw,
if (!fp->program.is_arb_asm) {
brw_nir_setup_glsl_uniforms(mem_ctx, nir, &fp->program,
&prog_data.base, true);
- brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir,
- NULL, prog_data.base.ubo_ranges);
+ if (brw->can_push_ubos) {
+ brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir,
+ NULL, prog_data.base.ubo_ranges);
+ }
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base);
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