Mesa (main): aco: Add validation for v_permlane instructions.

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Module: Mesa
Branch: main
Commit: 5713e059ea6f2c6ed4a95f58edf33648278e2532
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5713e059ea6f2c6ed4a95f58edf33648278e2532

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Fri May 28 21:56:50 2021 +0200

aco: Add validation for v_permlane instructions.

Previously there hasn't been any validation for these instructions,
but after shooting myself in the leg with it a few times, I decided
to add the validation now.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka at gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11072>

---

 src/amd/compiler/aco_optimizer.cpp |  6 +++++-
 src/amd/compiler/aco_validate.cpp  | 10 ++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp
index 51cd347561e..f44f4a3e725 100644
--- a/src/amd/compiler/aco_optimizer.cpp
+++ b/src/amd/compiler/aco_optimizer.cpp
@@ -745,7 +745,9 @@ bool can_apply_sgprs(opt_ctx& ctx, aco_ptr<Instruction>& instr)
           instr->opcode != aco_opcode::v_readlane_b32 &&
           instr->opcode != aco_opcode::v_readlane_b32_e64 &&
           instr->opcode != aco_opcode::v_writelane_b32 &&
-          instr->opcode != aco_opcode::v_writelane_b32_e64;
+          instr->opcode != aco_opcode::v_writelane_b32_e64 &&
+          instr->opcode != aco_opcode::v_permlane16_b32 &&
+          instr->opcode != aco_opcode::v_permlanex16_b32;
 }
 
 void to_VOP3(opt_ctx& ctx, aco_ptr<Instruction>& instr)
@@ -818,6 +820,8 @@ bool valu_can_accept_vgpr(aco_ptr<Instruction>& instr, unsigned operand)
    if (instr->opcode == aco_opcode::v_readlane_b32 || instr->opcode == aco_opcode::v_readlane_b32_e64 ||
        instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64)
       return operand != 1;
+   if (instr->opcode == aco_opcode::v_permlane16_b32 || instr->opcode == aco_opcode::v_permlanex16_b32)
+      return operand == 0;
    return true;
 }
 
diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index 57a61e5ded8..a86328ca372 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -286,6 +286,16 @@ bool validate_ir(Program* program)
                            "Wrong Operand type for VALU instruction", instr.get());
                      continue;
                   }
+                  if (instr->opcode == aco_opcode::v_permlane16_b32 ||
+                      instr->opcode == aco_opcode::v_permlanex16_b32) {
+                     check(i != 0 ||
+                           (op.isTemp() && op.regClass().type() == RegType::vgpr),
+                           "Operand 0 of v_permlane must be VGPR", instr.get());
+                     check(i == 0 ||
+                           (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
+                           op.isConstant(),
+                           "Lane select operands of v_permlane must be SGPR or constant", instr.get());
+                  }
 
                   if (instr->opcode == aco_opcode::v_writelane_b32 ||
                       instr->opcode == aco_opcode::v_writelane_b32_e64) {