Mesa (staging/21.1): radv: emit PA_SC_CONSERVATIVE_RASTERIZATION_CNTL only on GFX9+
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gitlab-mirror at kemper.freedesktop.org
Thu Jun 10 11:32:24 UTC 2021
Module: Mesa
Branch: staging/21.1
Commit: 23432781b00c1ca899610a3672cec543b0f37e51
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23432781b00c1ca899610a3672cec543b0f37e51
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jun 7 07:40:54 2021 +0200
radv: emit PA_SC_CONSERVATIVE_RASTERIZATION_CNTL only on GFX9+
This context register doesn't exist on older generations.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11210>
(cherry picked from commit 736893060f6984b5c8198ddbd491265f60de8548)
---
.pick_status.json | 2 +-
src/amd/vulkan/radv_pipeline.c | 40 +++++++++++++++++++++-------------------
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index f516996d1ad..9cbf496e2dc 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1156,7 +1156,7 @@
"description": "radv: emit PA_SC_CONSERVATIVE_RASTERIZATION_CNTL only on GFX9+",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 33b04955fb5..0a684234980 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4191,27 +4191,29 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_DX10_DIAMOND_TEST_ENA(1));
- /* Conservative rasterization. */
- if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
- pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
- S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
-
- if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
- pa_sc_conservative_rast |=
- S_028C4C_OVER_RAST_ENABLE(1) | S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
- S_028C4C_UNDER_RAST_ENABLE(0) | S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
- S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
- } else {
- assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
- pa_sc_conservative_rast |=
- S_028C4C_OVER_RAST_ENABLE(0) | S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
- S_028C4C_UNDER_RAST_ENABLE(1) | S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
- S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* Conservative rasterization. */
+ if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
+ pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
+ S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
+
+ if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(1) | S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_UNDER_RAST_ENABLE(0) | S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
+ } else {
+ assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
+ pa_sc_conservative_rast |=
+ S_028C4C_OVER_RAST_ENABLE(0) | S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
+ S_028C4C_UNDER_RAST_ENABLE(1) | S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
+ S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
+ }
}
- }
- radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
- pa_sc_conservative_rast);
+ radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
+ pa_sc_conservative_rast);
+ }
}
static void
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