Mesa (staging/21.1): aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7

[GitLab Mirror]

Module: Mesa
Branch: staging/21.1
Commit: e31f9c0883bf1c8bdf51ce05a72b8609110a2499
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e31f9c0883bf1c8bdf51ce05a72b8609110a2499

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Jun  7 15:19:59 2021 +0200

aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7

GFX6-7 are affected by a hw bug that prevents address clamping to work
correctly when the SGPR offset is used. Use the VGPR offset to fix it.

Fixes various hangs with dEQP-VK.robustness.robustness2.* on Bonaire.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11238>
(cherry picked from commit 3761d994f6de81d151b4709314f6ffc9b59f0908)

---

 .pick_status.json                              |  2 +-
 src/amd/compiler/README-ISA.md                 |  6 ++++++
 src/amd/compiler/aco_instruction_selection.cpp | 13 +++++++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 93a2283095d..32224979ca8 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -751,7 +751,7 @@
         "description": "aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md
index cb9d8da0298..c692fdf7e16 100644
--- a/src/amd/compiler/README-ISA.md
+++ b/src/amd/compiler/README-ISA.md
@@ -160,6 +160,12 @@ finish and then write to vcc (for example, `s_mov_b64 vcc, vcc`) to correct vccz
 
 Currently, we don't do this.
 
+## SGPR offset on MUBUF prevents addr clamping on SI/CI
+
+[See this LLVM source.](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp#L1917-L1922)
+
+This leads to wrong bounds checking, using a VGPR offset fixes it.
+
 ## GCN / GFX6 hazards
 
 ### VINTRP followed by a read with `v_readfirstlane` or `v_readlane`
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 594d195374f..65a23bbda08 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -5049,6 +5049,13 @@ void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_
    bool use_smem = dst.type() != RegType::vgpr && (!glc || ctx->options->chip_class >= GFX8) && allow_smem;
    if (use_smem)
       offset = bld.as_uniform(offset);
+   else {
+      /* GFX6-7 are affected by a hw bug that prevents address clamping to
+       * work correctly when the SGPR offset is used.
+       */
+      if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8)
+         offset = as_vgpr(ctx, offset);
+   }
 
    LoadEmitInfo info = {Operand(offset), dst, num_components, component_size, rsrc};
    info.glc = glc;
@@ -6230,6 +6237,12 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
    split_buffer_store(ctx, instr, false, RegType::vgpr,
                       data, writemask, 16, &write_count, write_datas, offsets);
 
+   /* GFX6-7 are affected by a hw bug that prevents address clamping to work
+    * correctly when the SGPR offset is used.
+    */
+   if (offset.type() == RegType::sgpr && ctx->options->chip_class < GFX8)
+      offset = as_vgpr(ctx, offset);
+
    for (unsigned i = 0; i < write_count; i++) {
       aco_opcode op = get_buffer_store_op(write_datas[i].bytes());