Mesa (main): aco: fix emit_mbcnt() with a VGPR mask

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Module: Mesa
Branch: main
Commit: 9162963f0abbc226b7e2caf897a93aa79bcb9b31
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9162963f0abbc226b7e2caf897a93aa79bcb9b31

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Thu Jun 10 11:07:31 2021 +0100

aco: fix emit_mbcnt() with a VGPR mask

Found by inspection. Should be possible with nir_intrinsic_mbcnt_amd.

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11295>

---

 src/amd/compiler/aco_instruction_selection.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 9ca92d4f7d3..66ac6854eff 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -142,7 +142,8 @@ Temp emit_mbcnt(isel_context *ctx, Temp dst, Operand mask = Operand(), Operand b
    Operand mask_hi(-1u);
 
    if (mask.isTemp()) {
-      Builder::Result mask_split = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), mask);
+      RegClass rc = RegClass(mask.regClass().type(), 1);
+      Builder::Result mask_split = bld.pseudo(aco_opcode::p_split_vector, bld.def(rc), bld.def(rc), mask);
       mask_lo = Operand(mask_split.def(0).getTemp());
       mask_hi = Operand(mask_split.def(1).getTemp());
    } else if (mask.physReg() == exec) {