Mesa (main): anv: Cache VB/IB in L3$ for Gfx12

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Module: Mesa
Branch: main
Commit: 6c345ddbe409af73d005beb6be4c529f249deea0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c345ddbe409af73d005beb6be4c529f249deea0

Author: Felix DeGrood <felix.j.degrood at intel.com>
Date:   Wed Mar 24 09:08:58 2021 -0700

anv: Cache VB/IB in L3$ for Gfx12

Gfx12 enables caching of Vertex and Index Buffers in L3.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>

---

 src/intel/blorp/blorp_genX_exec.h  | 4 ++++
 src/intel/vulkan/genX_cmd_buffer.c | 6 ++++++
 src/intel/vulkan/genX_gpu_memcpy.c | 3 +++
 src/intel/vulkan/gfx8_cmd_buffer.c | 3 +++
 4 files changed, 16 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index accfaa48a28..ddc9dfb66d1 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -379,6 +379,10 @@ blorp_fill_vertex_buffer_state(struct GENX(VERTEX_BUFFER_STATE) *vb,
    vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA;
    vb[idx].MaxIndex = stride > 0 ? size / stride : 0;
 #endif
+
+#if GFX_VER >= 12
+   vb[idx].L3BypassDisable = true;
+#endif
 }
 
 static void
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index ed92852a612..04eb12340b0 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3537,6 +3537,9 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
                .BufferPitch = stride,
                .BufferStartingAddress = anv_address_add(buffer->address, offset),
                .NullVertexBuffer = offset >= buffer->size,
+#if GFX_VER >= 12
+               .L3BypassDisable = true,
+#endif
 
 #if GFX_VER >= 8
                .BufferSize = size,
@@ -3726,6 +3729,9 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
          .MOCS = addr.bo ? anv_mocs(cmd_buffer->device, addr.bo,
                                     ISL_SURF_USAGE_VERTEX_BUFFER_BIT) : 0,
          .NullVertexBuffer = size == 0,
+#if GFX_VER >= 12
+         .L3BypassDisable = true,
+#endif
 #if (GFX_VER >= 8)
          .BufferStartingAddress = addr,
          .BufferSize = size
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c
index 3a48fd94327..8f83212b2d7 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -92,6 +92,9 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
          .BufferStartingAddress = src,
          .BufferPitch = bs,
          .MOCS = anv_mocs(cmd_buffer->device, src.bo, 0),
+#if GFX_VER >= 12
+         .L3BypassDisable = true,
+#endif
 #if (GFX_VER >= 8)
          .BufferSize = size,
 #else
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index b8baca4725d..59202fa8952 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -803,6 +803,9 @@ void genX(CmdBindIndexBuffer)(
       ib.MOCS                  = anv_mocs(cmd_buffer->device,
                                           buffer->address.bo,
                                           ISL_SURF_USAGE_INDEX_BUFFER_BIT);
+#if GFX_VER >= 12
+      ib.L3BypassDisable       = true;
+#endif
       ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
       ib.BufferSize            = buffer->size - offset;
    }