Mesa (main): anv: Replace DC Flush with HDC Pipeline Flush
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Tue Jun 15 13:47:24 UTC 2021
Module: Mesa
Branch: main
Commit: a49b145e8d59a7cdd6a16cc469c055f6746013f8
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a49b145e8d59a7cdd6a16cc469c055f6746013f8
Author: Felix DeGrood <felix.j.degrood at intel.com>
Date: Thu Mar 18 09:44:33 2021 -0700
anv: Replace DC Flush with HDC Pipeline Flush
HDC Pipeline Flush is the correct method for flushing HDC
pipeline on Gfx12+ HW. Continue using DC Flush for earlier HW.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
---
src/intel/vulkan/anv_blorp.c | 2 +-
src/intel/vulkan/anv_private.h | 14 ++++++++------
src/intel/vulkan/genX_cmd_buffer.c | 14 +++++++++++++-
3 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8f1ee0c71a6..ed1d4c685ef 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1517,7 +1517,7 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
- ANV_PIPE_DATA_CACHE_FLUSH_BIT |
+ ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT,
"before copy_to_shadow");
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 196668b535e..bf96b7b5851 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2451,6 +2451,7 @@ enum anv_pipe_bits {
#define ANV_PIPE_FLUSH_BITS ( \
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
+ ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
ANV_PIPE_TILE_CACHE_FLUSH_BIT)
@@ -2463,7 +2464,7 @@ enum anv_pipe_bits {
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
- ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
+ ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | \
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
@@ -2479,9 +2480,9 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
case VK_ACCESS_SHADER_WRITE_BIT:
/* We're transitioning a buffer that was previously used as write
* destination through the data port. To make its content available
- * to future operations, flush the data cache.
+ * to future operations, flush the hdc pipeline.
*/
- pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
break;
case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
/* We're transitioning a buffer that was previously used as render
@@ -2584,7 +2585,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
if (device->physical->compiler->indirect_ubos_use_sampler)
pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
else
- pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
break;
case VK_ACCESS_SHADER_READ_BIT:
case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
@@ -2610,11 +2611,12 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
/* Transitioning a buffer for conditional rendering. We'll load the
* content of this buffer into HW registers using the command
* streamer, so we need to stall the command streamer to make sure
- * any in-flight flush operations have completed. Needs
- * tile cache flush because command stream isn't L3 coherent yet.
+ * any in-flight flush operations have completed. Needs tile cache
+ * and data cache flush because command stream isn't L3 coherent yet.
*/
pipe_bits |= ANV_PIPE_CS_STALL_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_HOST_READ_BIT:
/* We're transitioning a buffer that was written by CPU. Flush
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 56db9848cc9..90811ea8eff 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -97,7 +97,11 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* clear depth, reset state base address, and then go render stuff.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+#if GFX_VER >= 12
+ pc.HDCPipelineFlushEnable = true;
+#else
pc.DCFlushEnable = true;
+#endif
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
#if GFX_VER == 12
@@ -2202,9 +2206,13 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
#if GFX_VER >= 12
pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
+ pipe.HDCPipelineFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
+#else
+ /* Flushing HDC pipeline requires DC Flush on earlier HW. */
+ pipe.DCFlushEnable |= bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
#endif
pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
- pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
+ pipe.DCFlushEnable |= bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
@@ -4979,7 +4987,11 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.RenderTargetCacheFlushEnable = true;
pc.DepthCacheFlushEnable = true;
+#if GFX_VER >= 12
+ pc.HDCPipelineFlushEnable = true;
+#else
pc.DCFlushEnable = true;
+#endif
pc.PostSyncOperation = NoWrite;
pc.CommandStreamerStallEnable = true;
#if GFX_VER >= 12
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