Mesa (main): anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT

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Module: Mesa
Branch: main
Commit: ef70388a3a183e83ab4a8fb059c83587de295cea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef70388a3a183e83ab4a8fb059c83587de295cea

Author: Felix DeGrood <felix.j.degrood at intel.com>
Date:   Wed Mar 17 19:46:41 2021 -0700

anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT

Gfx12+ PIPE_CONTROL bit for flushing HDC cache and memory
transactions to L3 cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>

---

 src/intel/vulkan/anv_private.h     | 6 ++++++
 src/intel/vulkan/anv_util.c        | 2 ++
 src/intel/vulkan/genX_cmd_buffer.c | 1 +
 3 files changed, 9 insertions(+)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5c61c121180..196668b535e 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2411,6 +2411,12 @@ enum anv_pipe_bits {
    ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
    ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT    = (1 << 12),
    ANV_PIPE_DEPTH_STALL_BIT                  = (1 << 13),
+
+   /* ANV_PIPE_HDC_PIPELINE_FLUSH_BIT is a precise way to ensure prior data
+    * cache work has completed.  Available on Gfx12+.  For earlier Gfx we
+    * must reinterpret this flush as ANV_PIPE_DATA_CACHE_FLUSH_BIT.
+    */
+   ANV_PIPE_HDC_PIPELINE_FLUSH_BIT           = (1 << 14),
    ANV_PIPE_CS_STALL_BIT                     = (1 << 20),
    ANV_PIPE_END_OF_PIPE_SYNC_BIT             = (1 << 21),
 
diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 0d171264667..b06ee760f70 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -121,6 +121,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits)
       fputs("+depth_flush ", stderr);
    if (bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT)
       fputs("+dc_flush ", stderr);
+   if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
+      fputs("+hdc_flush ", stderr);
    if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
       fputs("+rt_flush ", stderr);
    if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 787fde6495f..56db9848cc9 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -57,6 +57,7 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
    bits |= (pc->DCFlushEnable) ?  ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
 #if GFX_VER >= 12
    bits |= (pc->TileCacheFlushEnable) ?  ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
+   bits |= (pc->HDCPipelineFlushEnable) ?  ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
 #endif
    bits |= (pc->RenderTargetCacheFlushEnable) ?  ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
    bits |= (pc->StateCacheInvalidationEnable) ?  ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;